SU1386947A1 - Device for determining radioelectronic circuit operability range - Google Patents

Abstract

The invention relates to the field of instrumentation technology. A device for determining the operability range of electronic circuits comprises a block (B) 32, indications; generator of 2 clock pulses, divider 3 frequencies, transducers 7–10 perturbations; B, 14 analysis, logical B

Description

00 05; O

Nti

I - O

15, switches 4, 11 and 22, B 16 pulse shaping, B 33 controls, elements 17-17, and shertor 34, adder 28, counters 5 and 6, generator 12 pseudo-random codes, B 31 initial setup, decoder 23, register 24 thresholds, multiplexers 13, 25 and 26, demultiplexer 27, B 29 memory, digital-to-analog

138

Converter 50 and B 33 control — In the description of the invention, electric circuits of the adder 28, B 29 of the memory, B 33 of the control, generator 12 of pseudo-random codes are given. The device has an increased accuracy of determining the boundaries of the health areas by taking into account the effect of random disturbances. 7 ill., 1 tab.

The invention relates to instrumentation technology and can be used to monitor the health of electronic circuits.

The purpose of the invention is to improve the accuracy of determining the boundaries of health areas by taking into account the effects of random disturbances.

FIG. 1 shows a block diagram of the device; FIGS. 2 and 3 are timing charts of the device; . in (} "d. 4 is an adder circuit; Fig. 5 is a diagram of a memory block; Fig. 6 is a circuit of a control unit; Fig. 7 is a diagram of a pseudo-random code generator.

The device for determining the operability area of the electronic circuit 1 contains a generator 2 clock pulses, a divider 3 frequencies, the first switch 4, the first 5 and second 6 counters, the first 7, the second 8, the third 9 and the fourth 10 disturbance converters, the second switch 11,: generator 12 pseudorandom codes j first multiplexer. 13, analysis unit 14, logic unit 15, pulse shaping unit 16, first 17, second 18, third 19, fourth 20 and fifth 21 elements AND, third switch 22, decoder 23, threshold register 24, second 25 and third 26 multiplexers, demultiplexer 27, adder 28, memory block 29, digital-to-analog converter 30, initial setup block 31, display block 32, control block 33 and inverter 34,

The adder 28 contains a combinational adder 35, the third counter 36,

one-shot 37, the sixth element And 38 and one-shot 39-.

The memory unit 29 comprises a storage unit 40, a first 41 and a second 42 address decoder, and a write-read unit 43.

The control unit 33 contains four counters 44, first 45, second 46 and third 47 triggers, first button 48, first 49 and second 50 switches, second 51 and third 52 buttons, third 53 and fourth 54 switches, seventh 55, eighth 56, the girls 57 and the tenth 58 elements AND, first 59, the second 60 and the third 61 elements OR.

The pseudo-random code generator 12 contains the first 62, second 63, third 64 and quarter 65 digital code generators, eleven 66 and twelve 67 elements I. The generators 62-65 are based on feedback shift registers 68-71.

The generator 2 clock pulses connected to the input of the divider 3 frequency. First 7, second 8, third 9 and quarter 10 disturbance converters are connected by outputs to the corresponding outputs of the device, the inputs of which are connected to the corresponding inputs of analysis unit 14 connected by outputs to the corresponding inputs of logic unit 15, the output of which is connected to the first input of pulse shaping unit 16. The first and second outputs of the frequency divider 3 are connected to the same inputs of the first switch 4 connected by a control input to the first output of the control unit 33 and to the first inputs of the first 17 and second 18

And elements, output - with the input of the inverter 34, with the control input of the adder 28 and with the counting input of the first counter 5.

The installation input of the first counter 5 is connected to the installation input of the second counter bis second output of the control unit 33, transfer code to the second input element I 17 and counting input of the second counter 6 connected by the transfer output 18 to the second input second element I 18 and to the first input a control unit 33 connected by a third output to a first input of the third element AND 19 and a fourth output to a first input of a fourth element And 20. The output of the inverter 34 is connected to the second input of a pulse shaping unit 16 connected to the output a house with a summing input of the adder 28 and with the second inputs of the third 19 and fourth 20 elements And, the connected outputs with the first and second information inputs of the memory block 29.

A digital-to-analog converter 3 output is connected to the information input of the second switch 11 connected by the first, second and third outputs to the corresponding first, second and third signal inputs of the display unit 32 connected by the first and second control inputs with the outputs of the first 17 and second 18 elements I, Perv The second, third and fourth outputs of the initial installation block 31 are connected to the informational inputs of the same generator of pseudo-random codes 12 connected by a setup input to a setup input Registers 24, threshold values and the second output of the control unit 33, a first clock terminal

with the output of the first switch 4, the second pulses, the switching input of the third multiplexer 26, the first output of the control unit 33 and the control input of the first multiplexer 13 connected by the first and second outputs with the corresponding first and second address inputs of the memory block 29. The third and fourth outputs of control unit 33 are connected respectively to the first and second control inputs of the generator 12 pseudo-random codes and to the third and fourth inputs of the third switch 22 connected by a control input to the fifth exhaust output of the first counter 5, the counting input of the second counter 6 and the second input of the first element 17 and the third synchronized input with the transfer output of the second counter 6, the first input of the control unit 33 and the second input of the second element 18.

The first and second outputs of the generator 12 pseudo-random codes are connected to the inputs of the first 7 and second 8 disturbance converters and the first

and the second inputs of the first multilead control unit 33. Login register

0

five

0

five

0

Copy 13, connected by the third and fourth inputs with information outputs of the first 5 and second 6 counters, respectively. The third and fourth outputs of the generator 12 pseudorandom codes are connected to the inputs of the third 9 and fourth 10 perturbation converters. The adder input is connected to the output of the second multiplexer 25, the information inputs of the threshold value connected to the outputs of register 24, and the control inputs to the corresponding control inputs of the third multiplexer 26, demultiplexer 27, second switch 11, and outputs of the decoder 23 connected to the inputs of the third switch 22,

The subtracting input of the adder 28 is connected to the first output of the third multiplexer 26, the second output connected to the input of the digital-analog converter 30. The output of the adder 28 is connected to the input of the demultiplexer 27 connected to the first, second and third outputs respectively to the third, fourth and fifth information inputs of block 29 the memory connected to the first and second outputs with the same inputs of the third switch 22, and the third, fourth and fifth outputs with the first, second and third inputs of the third multiplexer 26.

The control output of the adder 28 is connected to the first control input of the memory unit 29 connected by a second control input to the output of the first element I 21 connected by a direct input to the output of the inverter 34 and the second input of the pulse shaping unit 16, and the inverse input to the third input of the formation unit 16

pulses, switching input three

A multiplexer 26, a first output of the control unit 33 and a control input of the first multiplexer 13 connected by the first and second outputs with the corresponding first and second address inputs of the memory block 29. The third and fourth outputs of control unit 33 are connected respectively to the first and second control inputs of the pseudo-random code generator 12 and to the third and fourth inputs of a third switch 22 connected by a control input to the fifth output of the 24 threshold values connected to the fifth output of the initial installation block 31 , and the sixth output of the control unit 33 is with the control input of the taler 2 sync pulses.

The device works as follows.

In the first mode, test signals are input to the input terminals of the test digital circuit 1, and a working area is determined, information about which is recorded in memory block 29.

: In the second mode, this information is periodically read from the memory block 29 and the image is displayed 1 of the operability area on the 2 | crane of the display unit 32.

; The test signal generation mode is divided into four period- Yes: a) initial setup b) impact of 4) on circuit 1 of two (I and II) perturbations, c) impact of three (I, II and III) disturbances; d) the impact of four | 1 (i, ii, iii and iv) disturbances. All of the above modes are implemented alternately.

The disturbances to the tested circuit 1 come from the outputs of the converters 7-10 disturbances. As disturbing influences, the supply voltage of the circuit can be used, the active and reactive load on the inputs and outputs of circuit 1, additive detector signals at the information inputs of circuit 1, etc. The input signals for transducers 7-10 ow - c) are random digital codes, 12 pseudo-random codes are generated from the outputs. Each of transducers 7-10 contains a digital-to-analog converter and a normalizing amplifier, which allows the input code to be converted to an analog disturbance value.

The test signal generation mode starts with the initial installation of the device blocks. Time point

No tp by signal Reset in the control unit 33 at its sixth output, the low level of the control signal Z is suppressed, which prohibits the generation of pulses in the generator 2 sync pulses (Fig. 26).

In block 31 of the initial setup, a set of four initial code values is performed for each series of aircrafts.

,,

0 5

0

five

About 5

five

0

0

five

impact conditions, as well as a set of parallel digital code containing three components: threshold values of the number of operation of circuit 1 for each of the three test modes. At time t, the signal Set in control block 33 at its second output signal Z fades (Fig. 2a), setting the counters 5 and 6 to zero and allowing the entry of the initial code values into the registers of the pseudo-random code generator 12 and entering the code of threshold values into register 24 thresholds. At the same time, at the third and fourth outputs of the control unit 33, zero levels of control signals Y and Y are established, prohibiting the passage of signals through the elements 19 and 20 to the memory block 29.

The generator 2 clock pulses imposes high frequency pulses to the input of the divider 3 frequencies. At one output of divider 3, the frequency of the pulses corresponds to the frequency of change in the magnitude of the first disturbing action, at the other output, the frequency corresponding to the display of the image on the display unit 32. In the generation mode, the zero level of the signal Zp at the first output of the control unit 33 prohibits the passage of pulses through the elements 17 and 18 to the synchronization inputs of the display unit 32, which is enabled. The passage through the element I 21 of signals to the block 29 of memory and the connection of the following parts: t is the code of switch 4 to the first one. 3 splitter output.

At time t, the Start signal in control block 33 is set to a single signal level Z and the generation of clock pulses in generator 2 begins (Fig. 26e). These clock pulses through divider 3 and switch 4 are passed to the first synchronous input of generator 12 and to the input of counter 5. During the time period to t5, the control signals U, U 00 correspond to only two disturbances I and II (Fig. 2c, d ). This is achieved by prohibiting the passage of sync signals to the third 64 and fourth 65 digital code generators in the generator of 12 pseudo-random codes.

At the same time, random sequences of codes are generated at the first and second outputs of generator 12.

the first and second disturbances (figs, 2h, and). At the same time, the counter 5 counts the number of generated codes. The zero level of the signal Zp connects the first two outputs of the generator 12 to the outputs of the multiplexer 13. As a result, the addresses of the cells in the memory block 29 are also determined by the codes determining the disturbing effects. under the influence of precisely these perturbations. When the counter 5 is filled, a signal appears at its transfer output (FIG. 2e), which, after being approved by the analysis unit 14, sigpets to the input of counter 6, and it counts the number of series of pseudo-random sequences generated at the first and second outputs of the generator 12,

At the first filling of the counter 6 at the time tg, a signal appears at its transfer output (Fig. 2g), which is fed to the first input of the control unit 33 and sets the control signal Y, equal to 1 (Fig. 2c), now resolved passing the clock signals through the element 66 at the input of the third digital generator 64 codes and at the third output of generator 12 a random sequence of disturbance codes III is formed with a frequency equal to the frequency of the signals at the transfer output of counter 5 (FIG. 2k).

At the second filling of the counter 6 at the time tg, a signal appears at its transfer output, which sets in the control unit 33

equal signal Y, equal to 1 (fig, 2d). Now in generator 12 the passing of clock signals through element 67 to the input of a digital code generator 65 is allowed and a random output is formed at the fourth output of generator 12, the levels of perturbing sources are disturbed by the frequency equal to the frequency of the signals at the output of the transfer of the counter 6 (Fig, 2l),

Thus, in the test signal generation mode, first two random disturbances I and II are formed with the same frequency of change. In this case, due to the different initial codes in the digital generators 62 and 63 codes and a different number of bits in the shift registers 68 and 69 of these generators, a random search is performed for possible combinations

50

55

actions and their memory cells in memory block 29. This allows simultaneously with the testing of circuit 1 to record an assessment of its operability in memory block 29.

To do this, in each clock cycle from the clock signal X from the output of the switch 4, after the address codes have been established, the contents of the selected memory cell will appear at the outputs of the memory block 29 at its outputs. The information in each cell of memory block 29 is recorded in three information fields and one

first and. second disturbances. In the period t, tg three disturbances act, and the enumeration of the values of the first two disturbances is repeated. Similarly, under the action of four disturbances, the enumeration of the values of the first three disturbances is repeated.

The analysis unit 14 produces a threshold control of the correct functioning of the circuit 1, analyzing the state for each of its outputs separately. When finding circuit parameters in the field

0

5 o

five

0

It is connected to the inputs of logic block 15, which implements the AND function, which generates at its output a signal that takes on a single value when radio electronic circuit 1 for all outputs is located in the operability area. This signal arrives at the first input of the pulse shaping unit 16, the second. the input of which comes the clock pulses, inverted by the inverter 34, and the third input - the control signal Zp. As a result, the output pulses of the block 16 indicate the operability of the circuit 1 at these disturbances (Fig. 3g).

To memorize the working condition of the circuit 1 under test, a matrix type memory 29 is used. The first output of the generator 12 pseudo-random codes in the mode of generating test signals is connected through the multiplexer 13 to the first address

Block 29 and determines the row of the matrix, the second output of the generator 12- to the second address input and determines the column of the matrix,

As a result, each value of the codes at the outputs of the generator 12 correspond to its levels of disturbing air.

actions and their memory cells in memory block 29. This allows simultaneously with the testing of circuit 1 to record an assessment of its operability in memory block 29.

To do this, in each clock cycle from the clock signal X from the output of the switch 4, after the address codes have been established, the contents of the selected memory cell will appear at the outputs of the memory block 29 at its outputs. The information in each cell of memory block 29 is recorded in three information fields and one

control field. The control field of the cell contains two bits of the identification code, in which the signals from the outputs of the AND 1U and 20 elements are recorded. fia, the first inputs of these elements are the control signals Y, and Yg, and the second inputs are the strobe signal from the output of the pulse shaping unit 16. If scheme 1 is operational at that time, then block 16 generates a pulse that permits the writing of the Y, Y code in the control field of the memory cell of block 29 and adds a unit to the code of the number of operations of the tested circuit 1.

The sync signal X also records the read code from the selected information cell of the memory into the counter 36 of the adder 28. In this case, the choice of the desired cell depends on the identification code Y Y, i.e. from the number of perturbations acting at the given moment on scheme 1. For this, the signals Y (and, from the control unit 33, through the switch 22, arrive at the decoder 23, at the origin of which a three-digit unitary code appears. The unitary code goes to the control inputs of the multiplexer 26, resulting in the subtractive input of the adder 28 passes the required information field of the contents of the memory cell containing the number of previous triggers of circuit 1 at given values of existing disturbances. If circuit 1 is operational and is currently testing When the same or x, the momentum on the leading edge

sa block 16 contents information

The high margin increases by 1 in the meter 36.

The inverse outputs of the counter 36 are connected to one input of the combinational adder 35 (FIG. 4), the other inputs of which receive a threshold value code for evaluating the performance of circuit 1. Three codes q, q, j, qj of threshold values are stored in register 24. The threshold value corresponding to the given combination of perturbations is read from register 24 through multiplexer 25. In the combinational adder 35 of the adder 28, the number of operations is subtracted from the threshold value. If the difference is negative, the output of the transfer of the combinational adder 35 shows a signal gating about 5

Q

about 5 Q

35

40

45

55

walking through the element 38 of the pulse C of the output of the one-shot 37, which is triggered by the signal from the output of block 16. As a result, the signal Zg of the identification code write Y, Y is formed in block 29 of the memory. Therefore, with. If the number of triggers of the specified threshold scheme is exceeded, the signal Zg indicates the operability of circuit 1 for a given number of disturbing influences. Then, by the signal Z (Fig. 3, 3), the identification code YjYj (Fig. 5) is written into the control Cell field of the memory block 29 (Fig. 5), which shows the greatest number of perturbations in force at which the test circuit 1 is still operational.

Code of the number of operations of circuit 1 from the direct outputs of the counter 36 of the adder

28 through the demultiplexer 27, controlled by the decoder 23, enters the corresponding information field of the selected memory cell of block 29 by the recording signal from the output of the AND element

21 (Fig. 3 and 5).

Thus, the test signal generation mode consists of three periods: the first period is the action of two disturbances, the identification code Y, Y 00, the second period t, the action of three disturbances, the identification code Y (Yj, 10, the third period the action of four disturbances, the code Y, Y2 11. The third period ends with the Reset signal in control unit 33. After this, the signal Z.O and the generation of clock signals X stop. In control unit 33, preparation is made for the information reading mode. For this, button 48 (FIG. 6) is transferred to the Output position.

Information is output in two sub-modes: 1 and 2. In sub-mode 1, the information field of the memory cell that reads the last value of the identification code recorded in the control field of this cell is read. For this purpose, the single level of the control signal Zu at the fifth output of the control block 33 connects to the output of the switch 22 the first and second outputs of the block

29pam tee. The output region of operability in this case corresponds to the effect of the greatest number of disturbances, in which circuit 1 is operable at given values of disturbances.

In submode 2, it is possible to output a health region for a given number of disturbances set by the operator in control block 33. For this Z; is set to O and the outputs of the switch 22 are connected to the outputs of block 33, on which the set values of the identification code are set using the switches 53 and 54 (Fig. 6).

The information reading mode starts on the Start signal in the control unit 33. The unit level of the signalZP connects to the switch output

4 second divider output 3 frequencies

la

РЗ

at which frequency of clock pulses

corresponds to the frequency of displaying image points in display unit 32. The output codes of counters 5 and 6 are used to address cells in the accumulator of block 29 and are connected to its address inputs via multiplexer 13. In read mode, the ZP control signal from the output of control block 33 switches the output of information through multiplexer 26 to the outputs connected to the digital-to-analog converter inputs 30o. The process of writing to the memory block 29 in this mode is blocked by the inverse input of the AND 21 element and by the prohibition of the generation of pulses by the pulse shaping unit 16.

From the outputs of block 29, parallel ID codes come into converter 30 and contain information about the operability of electronic circuit 1. The output voltage of converter 30 is fed to the input of switch 11, to the control inputs of which is supplied a unitary identification code from the outputs of the decoder 23. In As a result, the brightness of the image point displayed at a given moment is determined by: a) in submode 1 - the total number of operations of circuit 1 under the action of two, three and four disturbances; b) in submode 2 - the number of operations of circuit 1 when perturbations corresponding to the identification code specified in the control block 33. The color of the point depends on the number of perturbations in force and is presented in the table.

five

0

five

five

0

0

five

0

five

Since the brightness of the image point is proportional to the number of operations of the circuit 1, the operator’s perception of brightness should not depend on the color of the health area. For this purpose, the switch 11 contains in each channel the normalizing amplifiers, the gain factors of which are determined from the relative visibility curve so as to ensure the same perception of the different color zones of the working area.

FIG. 4 shows the possible execution of adder 28. Counter 36 serves to increase the number of circuit triggers by 1 if circuit 1 is operational and at that time. The code of the number of operations is recorded in the counter 36 by the information inputs D, -D under the action of the inverse signal C, formed from the sync signal X with a delay on the one-oscillator 39.

If a pulse appears at the output of block 16, it enters the counting input of counter 36 and increases its content by 1 with a leading edge. If circuit 1 is not operational, the code in counter 36 does not change. In the combinational adder 35, the number of operations is compared with a threshold value. The single-oscillator 37 delays the signal from block 16 to the input element And 38 in order to have time to occur addition in the counter 36. The transfer signal P at the output of the adder 35 occurs when overflow, t, e. In the event that the number of trips of circuit 1 becomes greater than the threshold value. This is necessary to increase the reliability of information about the health of the tested circuit 1.

FIG. 5 shows the possible execution of memory block 29. Memorization of information occurs in the drive

40. The address decoder 41 is used to select the rows, and the address decoder 42 is used to select the columns. The information from the selected cell is read by the sync X signal. The control field bits go to the inputs of the switch 22, and the cell information field bits go to the inputs of the multiplexer 26. The control of the multiplexer 26 is produced by the control code read in the same clock cycle, therefore the recording signal into the counter 36 of the adder 28 is delayed by the required amount by the single vibrator 39. The writing of the identification code to the accumulator 40 is effected by the signal Zg. The entry in the information fields of the cells is effected by signals X with the output AND gate 21,

FIG. 6 is a block diagram of the control unit 33. Operation begins with a signal reset from button 48, while counter 44 and triggers 45-47 are set to zero and zero level ZH is turned off at the sixth output of block 33. Switch 49 is switched to the Test position and allows passage to counter 44 transfer signals from the output of the counter 6. Signal Setting from the button 52 at the second output of the block 33 signal Zo, which is used to record the initial codes in the generator 12 and the register 24 threshold values c

On the Start signal from button 51, trigger 47 is set to one. In the first test period, push-pull triggers 45 and 46 generate the control code YjY 00. The first signal from the transfer output of counter 6, which enters the block 33, triggers 45 to one. and block itself on the input (Y, Y, j 10 code). On the second signal at the input of block 33, a trigger 46 is set to one and also self-blocking (code Y, Y2 11). Counter 44 reads a series of test sequences from the transfer signals of counter 6. When counter 44 overflows, a reset signal is generated and the test signal generation mode is terminated. In addition, the generation mode can be stopped by the operator when the Reset button 48 is pressed.

In read mode 1: this information switch 49 is set to the Output position and, according to the Start signal, the reading process begins. The identification code in submode 2 is set using switches 53 and 54. And elements 57 and 58 are locked at a low level from switch 50.

In Fig about 7 shows the possible execution of the generator 12 pseudo-random codes. Digital code generators 62-65 are set to the initial state by the signal ZP, with an echo, codes from the outputs of the initial installation unit 31 are recorded in them. Digital code generators are made on the basis of shift registers with feedback, the synchronization of shifts is made by signals on the generator clock signals 12 Vi Vi and 67 elements prohibit the passage of clock pulses during the corresponding test periods.

Claims (1)

Claims of invention A device for determining the operability area of electronic circuits, containing a display unit, a clock generator, connected to the input of a frequency divider, first, second, third and fourth disturbance converters connected by outputs with corresponding outputs, outputs of the device, the inputs of which are connected to the corresponding inputs of the analysis unit connected by the outputs to the corresponding inputs of the logic unit, the output of which is connected to the first input of the pulse shaping unit, the first and second outputs de A frequency switch is connected to the same inputs of the first switch connected by a control input to the first output of the control unit and to the first inputs of the first and second elements I, the output to the input of the inverter, to the control input of the adder and to the counting input of the first counter connected by the installation input with the installation input of the second counter and with the second output of the control unit, the transfer output - with the second input of the first element And and with the counting input of the second counter connected by the transfer output with the second input of the second The first element and the first input of the control unit connected to the first input of the third element and the fourth output to the first input of the fourth element I, the output of the inverter connected to the second input of the pulse shaping unit connected to the summing input of the adder and the second inputs the third and fourth And elements connected by outputs to the first and second information inputs of the memory block, a digital-analog converter, an output connected to the information input of the second switch, the first, second and third outputs with the corresponding first, second and third signal inputs of the display unit connected by the first and second control inputs to the outputs of the first and second elements AND, respectively, characterized in that, in order to improve the accuracy of determining the boundaries of health areas, it includes a pseudo-random code generator, an initial setup block, a third switch, a decoder, a threshold register, first, second and third multiplexers, a demultiplexer, and the fifth element AND, with The first, Q ka memory, connected by the second control of the second, third and quarter outputs of the initial setup block is connected to the same information inputs of the pseudo-random code generator connected by the setup input to the setup input of the threshold register, and the second output of the control unit, the first synchronous input to the output of the first switch, the second sync input. - with the transfer output of the first counter, the third sync input - with the transfer output of the second counter, the first and second outputs of the pseudo-random code generator They are connected respectively to the inputs of the first and second disturbance converters and the first and second inputs of the first multiplexer connected by the third and fourth inputs to the information outputs of the first and second counters, respectively, the third and quarter outputs of the pseudo-generator 35 40 45 50 The output input with the output of the AND gate connected directly to the output of the inverter and the inverse input with the third input of the pulse mapping unit is switched by the input of the third multiplexer. the first output of the control unit by the equalizing input of the first mult connected to the first and second turns with the corresponding first second address inputs of the block; the third and fourth outputs of the controlling block are connected according to the first and second controllers B5 of the pseudo-random code generator by the third and fourth inputs of the third switch connected by the control with the fifth output of the control unit connected by the sixth in with the control input of the chromopulse generator, the input of the register of the th values is connected to the fifth in random codes are connected by an appropriate setup block. with the inputs of the third and fourth disturbance converters, the input of the adder is connected to the output of the second multiplexer, the information inputs connected to the outputs of the threshold value register, and the controlling inputs to the corresponding control inputs of the third multiplexer, demultiplexer, second switch and the decoder outputs connected to the inputs with the outputs of the third switch, the subtracting input of the adder is connected to the first output of the third multiplexer, the second code connected to the input of the digital-analog converter, the adder's output is connected to the input of a demultiplexer connected by the first, second and third outputs respectively to the third, fourth and fifth information inputs of the memory block connected to the first and second outputs with the same inputs of the third switch, and the third, fourth and fourth the fifth outputs - with the first, second and third inputs of the third multiplexer; the control output of the adder is connected to the first control input of the block 0 five 0 An input input with an output of an And element connected to a direct input with an inverter output and an inverted input to a third input of a pulse shaping unit, a switching input of a third multiplexer, a first output of a control unit and a control input of a first multiplexer connected by the first and second the outputs with the corresponding first and second address — inputs of the mother block; the third and fourth outputs of the control block are connected respectively to the first and second control b5 soda of the pseudo-random code generator and from tr The third and fourth inputs of the third switch, connected by a control input to the fifth output of the control unit, connected by a sixth output to the control input of the clock generator, the input of the threshold register is connected to the fifth output ° 0 SI, s l r y d / fieoexoe ecv.s ffepexac C.B , League / Y / l8я .г gsk you are z gsk vbtsL gsk and FIG. g Out . 25 Out 5l. t 35 ST BUT D 7 36 SM 35 Zs On bohod dmmult 27 8y / h.Z soup 16 Compiled by V.Savinov Editor P.Geershi Tehred L. Serdyukova Proofreader S.Shekmar Order 1A93 / 45 Tir.azh 772 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk yab., d. 4/5 .7 Subscription