KR930000160B1 - Test system which evaluates ability in digital integrated circuit - Google Patents

Abstract

The test system having a high speed and a high accuracy comprises: a control signal group (38) controlling the test speed, the input timing and the gathering timing of test results; a controller (31) generating the pattern for testing and storaging the test results; a distributor (34b) and a generator (34a) generating the high speed pulse; a DC voltage control and voltage source (35) generating the test logic type decision signal setting input/output function of test pattern; an input buffer (32) providing the pattern for testing to an object (36); an output buffer (33) providing the test results obtained from the object to the controller (31).

Description

Test System for Performance Evaluation of Digital Integrated Circuits

1 is a block diagram of a test system for performance evaluation of a conventional digital integrated circuit.

2 is a block diagram of a high speed test pattern generator in a conventional performance evaluation test system.

3 is a block diagram of the present invention.

4 is a block diagram of an input / output buffer of the present invention.

5 is a circuit diagram of an input / output buffer of the present invention.

Figure 6 is a block diagram of a high speed clock generation and distributor of the present invention.

Figure 7 is a waveform diagram according to the input and output state of the high-speed clock generation and divider of the present invention.

8 is a detailed block diagram of the fast clock distributor of the present invention.

9 is a functional block diagram for explaining a process of determining the logical type of the measurement pattern of the present invention.

* Explanation of symbols for main parts of the drawings

31: controller 32: input buffer

33: output buffer 34: high speed clock generator and divider

36: measuring object

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a tester for performance evaluation of a digital integrated circuit, and more particularly, to a functional test system for performance evaluation of a digital integrated circuit which performs performance evaluation at a high speed and corrects the result at a measurement speed. In general, the operation speed of a high speed digital integrated circuit reaches several G bps, so it is well known that a test system for evaluating the operating performance of a high speed digital integrated circuit must meet the following requirements.

First: It should be possible to apply the measurement pattern to the input terminal of the measurement object at the actual operating speed of the digital integrated circuit to be evaluated.

Secondly, the timing of the input measurement pattern should be precisely controlled. In this case, the accuracy of timing should be 100psec or less for the measurement of integrated circuits with G bit operation speed.

Third: The operation logic of the digital integrated circuit to be measured should be able to apply the measurement pattern,

Fourth: It should be possible to collect or evaluate the measurement results output from the measurement object at the measurement speed.

Fifth: It should be possible to measure the power supply function and DC operating characteristics required by the measurement target.

Therefore, in the related art, a test system of a digital integrated circuit as shown in FIG. 1 (S90 of FAIRCHILD, J937 of TERADYNE, and DIC-8402 of ANDO) was used. The measurement pattern control and the compressor 1 and the pattern generator 2 equipped with the measurement pattern storage memory 1a output the measurement pattern under the control of the main computer 3 to be input to the time controller 4, In the time controller 4 in which the clock is input from the signal generator 5 for time control, the input data is input with the timing adjusted by the measurement pattern amplitude controller 6, and the measurement logic type in the measurement pattern amplitude controller 6 is inputted. (logic type) is converted into the measurement object (7).

The input data measured while passing through the measuring object 7 is collected by the output data detector 9 to which the output of the reference voltage controller 8 is applied simultaneously with the measurement pattern amplitude controller 6, and the output data detector 9 The output data outputted from is input to the bad data collection memory 10 or the time comparator 11.

The time comparator 11 receives the time control signal of the time control signal generator 5 and compares it with the output data, and then outputs the time comparison result to the host computer 3 while outputting the bad data to the bad data collection memory 10. Let's do it.

As described above, conventional digital signal patterns are incident on a measurement object at a predetermined timing, and responses thereof are collected in real time, and the operational characteristics of the measurement object are determined by comparing with a given reference expected response pattern.

However, the test system as described above has an advantage that the source can have an infinite pattern depth using a pattern generator using a memory memory having a complex control signal or a pattern generator by a logical operation. Complex hardware has made it difficult to generate high accuracy timing characteristics and high speed test patterns.

In order to solve this problem, the signal input / output speeds of the pattern generating means and the pattern receiving means should be faster than the operating speed of the measurement object.

In order to meet this demand, a test pattern is generated at a high speed by using a buffer using RAM multiplexed with input and output in time as shown in FIG.

That is, a plurality of RAMs 21, 21a, 22, 22a, 23, 23a, 24a and 24a to which the RMA control signals output from the selection signal generator 20 are inputted. ), Four pairs of outputs are respectively input to the multiplexers 25, 25a, 26, and 26a, and two pairs of multiplexers to which the third select signal select3 of the select signal generator 20 is input. A pair of multiplexers 27 outputted to a pair of multiplexers 27 and 27a at 25, 25a, 26a and 26a, respectively, and to which a second selection signal select2 is input, In 27a, the first select signal select1 is input to the multiplexer 28 to which the high speed output signal is output.

However, since the input and output time points are determined by the RAM control signal and the selection signals (select1, 2, 3) supplied by the selection signal generator 20 by such a buffer, a special technique is used when assembling the hardware for accurate timing control. High-speed operation in the 1 GHz band requires a large number of RAMs and a plurality of multiplexers (MUXs) for one measurement terminal (8 RAMs per measurement terminal for a high-speed RAM with 8 nsec call time). And three-stage multiplexers), and there is a problem that the timing inaccuracy is increased.

Accordingly, an object of the present invention is to provide a test system for evaluating the performance of a digital integrated circuit, in which the performance evaluation is performed accurately and at very high speed, and the result can be collected according to the speed.

To this end, the present invention is to evaluate the operation performance of the digital integrated circuit, the input and output buffers using the SISO shift register (Serial Input Serial Oatput shift Resister), the input and output logic value of the buffer drive under the control of the DC voltage source By enabling the control, the performance evaluation of digital integrated circuits can be evaluated with high speed and high accuracy.

The present invention is described in detail based on the accompanying drawings as follows.

3 is a block diagram of the present invention, the measurement pattern of the control signal group 38 of the controller 31 for controlling the measurement speed, measurement logic type, measurement pattern, input timing and measurement result collection timing of the system N measurement patterns (corresponding to the test pattern depths of the input and output buffers), which are denoted by N, are drawn into the input buffer 32 as the input data 37 and stored.

At this time, the input buffer 32 has a control signal group 38 of the measurement logic diagram controller 31 determined by the high-speed DC voltage control controlled by the control signal group 38 and the measurement logic decision signal of the voltage source 35. The timing specification is determined by this, and a high speed input / output buffer drive provided from the high speed clock generator and divider 34 is input in accordance with the N period of the clock.

Subsequently, the N measurement patterns 37 of the input buffer 32 are incident on the measurement object 36 at a high speed clock generation and the driving clock speed 40 of the distributor 34.

The measurement result 43 emitted from the measurement object 36 by the measurement pattern is collected at an interval corresponding to one period of the drive clock by the output buffer 33 driven at the drive clock speed 41.

The release time and the measurement result of the measurement patterns of the input and output buffers 32 and 33 are determined by a high speed clock generation and clock delay generator built in the divider 34, and the output buffer 33 The measurement result collected at includes information on an operation characteristic result and a timing characteristic of the measurement object 36.

The information collected in the output buffer 33 is transferred to the controller 31 in the process of introducing a new N-period measurement pattern, stored in its memory, and compared with the expected measurement result generated in the controller 31. Thus, the characteristic of the measurement object 36 is judged.

4 and 5 show the input and output buffers, and a plurality of D flip-flops 40a, 40b, 40c,... (40n-1) As the clock terminal of the high speed input / output buffers 32 and 33 including the SISO shift register composed of 40n, the high speed clock and the low speed clock are inputted through the OR gate OR. The data applied at a low speed to the input terminal D is output to the output terminal Q at a high speed. Therefore, the control of the input and output is determined by the driving clock, so that the data is stored in other memory devices (ROM) and (RAM, etc.). Compared to this, it is easy to control the input and output during the high speed operation.

6 and 7 show the high speed clock generator and divider 34 of FIG. 3, in which the high speed buffer drive output is output from the high speed clock generator 34a to which a source clock and a clock trigger are input. The measurement object clock divider 34b, the high speed input buffer clock divider 34c, and the high speed output buffer clock divider 34d are input to output the measurement object clock, the high speed input buffer clock, and the high speed output buffer clock, respectively.

Therefore, the N cycles generated by the high speed clock generator are properly amplified and distributed to the clock stages of the input and output buffers with the timing required for each clock. The clock delay time is transmitted to the controller 31. Is determined by

7 shows an operation characteristic of cutting the clock of N periods from the source clock (source clock) by the clock trigger in the high speed clock generator 34a.

8 is a detailed block diagram of the high-speed clock dividers 34b, 34c, and 34d shown in FIG. 3, and signals inputted to the driving amplifier 34A from each other are controlled by a fine time controller 34B and a coarse time controller. Output via the output amplifier 34D via 34C) adjusts the distribution of the high speed clock and the timing of application to the buffer.

FIG. 9 is a block diagram for explaining the operation of controllable DC voltage control and a voltage source (hereinafter referred to as 35 in FIG. to be.

The fixed logic low speed measurement pattern 37 is a variable logic high speed via an optical coupler 32a of the high speed input buffer 32 and a serial input aerial output shift register 32b. In the controllable DC voltage source 35 to which the measurement pattern is output and the power control signal is input, the high speed input buffer 32 supplies the input buffer driving DC power, and the high speed output buffer 3 outputs the driving DC power supply for the output buffer, respectively. A serial input serial output (SISO) shift register 33a of the high speed output buffer 33 to which the DC power supply 46 for the measurement object 36 is input while inputting, while the high speed measurement data 43 of the variable logic type is input. ) And the optical coupler 33b output fixed logic slow measurement data 39.

As such, the controllable DC voltage source 35 adjusts the power supply voltages required for the operation of the input and output buffers 32 and 33 to make the logic type necessary for the measurement.

Therefore, in the performance evaluation of the digital integrated circuit, the input and output buffers using the serial input serial output shift register are controlled so that the input and output are controlled while controlling the frequency and application time of the driving clock. It can be seen that the input and output logic values are controlled by the control of the output buffer and the DC voltage source for driving the buffer, thereby performing the performance evaluation of the digital integrated circuit with high accuracy.

Claims (2)

A test system for evaluating the performance of a digital integrated circuit, generating a control signal group 38 and a measurement pattern for controlling the measurement speed, the measurement logic type, the input timing, and the collection timing of the measurement results, respectively, A controller 31 for storing a result, a fast clock generator and divider 34 triggered by the controller 31 to generate a predetermined number of high-speed pulse trains, and a variable logic value measured by the controller 31 A high speed DC voltage control and voltage source 35 for generating a measurement logic decision signal for setting a pattern input / output function, and the high speed DC voltage control after storing the measurement pattern provided at a low speed from the controller 31; An input buffer 32 driven by the voltage source 35 and the high-speed clock generator and divider 34 to provide the measurement object 36 at high speed, and in response to the measurement pattern An output buffer 33 which receives and stores the measurement result provided from the measurement object 36 at a specific timing in real time and is controlled by the controller 31 to provide the measurement result to the controller 31. Test system for performance evaluation of a digital integrated circuit comprising a. 2. The input buffer 32 and the output buffer 41 each comprise SISO shift registers 32b and 33a driven by a high speed clock provided from the high speed clock generator and divider 34. Test system for performance evaluation of digital integrated circuit, characterized in that.

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