SU1383341A1 - Device for modulo m sub "i"(m sub "i" equals 1,n) addition and subtraction of numbers - Google Patents

Abstract

The invention relates to automation and computing and can be used in systems and devices functioning in the system of residual classes. The purpose of the invention is to expand the functionality by implementing module operations for a set of modules n, -.

Description

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The modular operations of addition and subtraction are implemented for a set of modules from m, 2 to t ,,, where u is the maximum specified module that the device operates in, containing the first 1 and second 9 information inputs, the first 2 and second 10 input registers, the decoder 3 , key elements 4, first 5, second 25 and third 29 .... groups of elements And, first 6, second 13 and third 31 elements OR, output register 7, output 8, first 11, second

12, third 19 and fourth 20 elements And, receive register 14, comparison circuit 15, pulse counter Ih, input 17 of the pulse generator, pulse generator 18, frequency multiplier 21, ring shift register 22, input 23 of the indication of the addition operation, input 24 through - a sign of a subtraction operation, a device control bus 26, a group of gates 27, a group of adders 28 modulo m, a PINE 30 of the feed of modules m; . I il.

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The invention relates to automation and computing and can be used in systems and devices, functioning in the system of residual classes.

The purpose of the invention is to expand the functionality by implementing modular operations of addition and subtraction for a set of modules of hectares, 2dot (the maximum module in which the device operates).

The drawing shows the functional diagram of the device for. addition and subtraction of numbers modulo m -.

The device contains the first information input 1 of the device, the first input register 2, the decoder 3, - the group of key elements 4, the first group of elements AND 5, the first element OR 6, the output register 7, the output 8 of the device, the second information input 9 of the device, the second input register 10, the first M and second 12 elements And the second element OR 13, the receiving register 14, the circuit 15 is compared. No, pulse counter 16 pulse start input 17 of pulse generator 18, third 19 and fourth 20 elements AND, frequency multiplier 21, ring shift register (DAC) 22, sign feed input 23 of the add operation, sign 24 input of the subtraction sign, second a group of elements And 25, inputs (bus) 26 control device, the fourth group

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elements And (gates) 27, a group of adders 28 modulo HP; , the third group of elements And 29 at the entrances (ishny)

30 submission of the values of the modules and- (i 1, p), the third element OR 31.

The device works as follows.

The first operand a; is supplied to the first input, and the second operand / 3 to the second input 9; . In the DAC 22 bits, the first row of the modular addition (subtraction) table is recorded (a „4-jJ J nod п, From the output of the deprafrater 3, the signal corresponding to the value a; in the unitary code, it goes to the first input of the a; -th key element 4 The signal corresponding to the attribute of the module m (i 1, p), on the i-th bus 26, opens ie the elements AND 25 and 29.

In this case, the modulo t of the first input of the adder 28; enters the second operand | 5; and to the second input of this adder via the corresponding i-bus 30 through the i-th open element I 29 is the value of I ;, and from the output of this adder to the input of the element S1I

31 value n arrives; - / 3; j. At the same time, the output signal of the i-element of the AND 25 closes the i-th valve 27, thus forming a circuit for passing the content of the DAC bits 22, realizing the operation of adding (subtracting) the numbers modulo m -. The device is triggered by the signal 17, and from the output of the generator 18, the pulses through the element 19, the multiplier 21 arrive at the shift inputs of the bits of the DAC 22, simultaneously from the output of the generator 18 through the elements 20 and the pulses arrive at the input of the counter 16. 14 and the counter 16, the output signal of the comparison circuit 15 closes the elements AND 19 and 20 and opens the elements AND 5 and the key elements 4, In the presence of a bus signal 23 (the operation code) from the output of the register 10, the opera through the open element I 1 1, the element OR 13 enters register 14, and in the presence of a signal rshna 24 (subtraction operation code) from the output of the i-ro adder 28, the value of p t; - R; through the elements OR 31, the open element AND 12, the element OR 13 enters the register 14, In this case, the bits of the DAC 22 are shifted along the formed contour (by this module AND;) by Р ;-( YLI;) of the bits against clockwise, From the output of the a; -th bit of the COP 22, the result of the operation through the open a, -, and element AND 5, the element OR 6 enters the input of the register 7,

Claims (1)

Invention Formula A device for adding and subtracting numbers modulo m; (t j 1, p) containing a reception register, a descrambler, a ring shift register, a group of key elements, a pulse generator, a frequency multiplier, a pulse counter, a comparison circuit, the first and second elements OR, the first group of elements is AND, the first, second, third and fourth elements AND, while the first information input of the device is connected to the input of the decoder of the output of which is connected to the first inputs of key elements whose outputs are connected to the first inputs of the elements AND first The second group, whose output through the first element OR is connected to the output of the device, the second information input of the device is connected to the first input of the first element AND, the output of which simultaneously with the output of the second element AND through the second element OR connected to the input of the receiving register, the output of which is connected to the first the input of the comparison circuit, to the second input of which the output of the pulse counter is connected, and the device start input is connected to the input of the generator g 0 5 0 five 0 five 0 five pulses, the output of which is connected to the first inputs of the third and fourth elements AND, whose outputs are connected to the inputs of the frequency multiplier and the pulse counter, respectively, and the output of the comparison circuit is connected to the inverse inputs of the third and fourth elements AND, to the enable inputs of key elements and elements And the first group, and the output of the frequency multiplier is connected to the shift inputs of the bits of the ring shift register, the output of which bits are connected to the third inputs of elements AND of the first group, to the second inputs of the first The second and second elements are connected to the feed input of the operation characteristic, respectively, of adding and reading, characterized in that, in order to extend the functionality by implementing modular add operations and reading for a set of modules from and, 2 to n "(d1 is the maximum module value), the second group of () -th element AND, a third group of n elements AND, the fourth group of () elements I, and a group of n adders modulo III are entered; and the third element OR, and the output of the bit of the ring shift register is connected to the first inputs of elements AND of the second group, to the second inputs of which the connection corresponds to the control input of the device, and the output K-th (to 1, t-2) - And the second group is connected to the inverse input of the K-th element And the even-right group and to the second input of the K-th digit of the ring shift register, the output (Id-O-th element And the second group is connected to the highest bit of the ring shift register, output t -th (6 p - 1, 2) bit annular shift Istra via the first input (Jl) -ro of the element And the fourth group is connected to the first input (Jl) -ro of the ring shift register, and the output of the first bit of the ring shift register is connected to the first input of the lower (zero) bit of the ring shift register , the second information input of the device is connected to the first inputs of adders modulo n, to the second inputs of which are connected - the outputs of the corresponding elements AND of the third group, to the first inputs of which are connected inputs 5113833416 giving the corresponding values to modul d. through the third element OR Lei ;, and to the enabling inputs are connected to the first input of the second the corresponding inputs of the control of the device element I. is a device, and the outputs of the adders are