SU1381716A1 - Delta decoder - Google Patents

Abstract

The invention relates to automation and communication technology. Its use in information systems of rv allows to increase coding accuracy by expanding the frequency band of the encoded signal. The delta coder contains a comparator 1, trigger 2, shift register 3, elements AND 4-7, element OR 8, counters 10, 11, fixed memory block 13, equivalence element, multiplexer block 15, decoders 16-18, reversible counter 19, the buffer registers 22, 23, the arithmetic logic unit 24, and the digital-to-analog converter 25. By introducing the trigger 9, the counter 12, and the multiplexers 20, 21, an optic selection of the quantization step is provided depending on the frequency composition of the encoded signal. 2 Il. i (L

Description

The invention relates to automation and communication technology and can be used in information transmission systems.

The purpose of the invention is to improve the coding accuracy by expanding the frequency band of the encoded signal.

FIG. 1 is a functional diagram of a delta coder; FIG. 2 shows time diagrams of his work.

The delta coder contains a comparator 1, the first trigger 2, the shift register 3, the first to fourth elements AND 4-7, the element OR 8, the second trigger 9, the first to third counters 10-12, the permanent memory block 13, the equivalence element 14 , block 15 multiplexers, the first - the third decoders 16-18, the reversing counter 19, the first and second multiplexers 20 and 21, the first and second buffer registers 22 and 23, the arithmetic logic unit (ALB) 24, the digital-to-analog converter ( DAC) 25, information and contact inputs 26 and 27 and output 28.

The second and third decoders 17 and 18 serve to indicate that the reversible counter 19 reaches N and N, respectively, some numbers indicating that the delta coder is working with either too large or too small quantization steps, because of which ka noise power either quantizing or overloading.

FIG. 2 are designated: and - clock sequence of impulses with frequency f (-;

b - output signal Y (t) of the delta coder;

in - signal B (t) at the output of the element 8 OR;

g - signal S (t) at the output of the second trigger 9; "

d, g-signals С, о (t), С i, Ct), ...,. . . , C, I, (t) at the first n outputs of the first decoder 16;

h, k — signals K, 0 (t) ,, (t),, ..., Kn (t) at the inverse outputs of the first n bits of the first buffer register 22;

l, n - signals (t) C, (t), ..., ...,, (t) at the second n outputs of the first decoder 16;

o, p are the signals (t), ..., K,}, (t) K (t) of the direct outputs of the second n bits of the first buffer register 22;

C, t - signals M, (t), M (t) at the outputs of the first and second multiplexers 20 and 21;

y is the signal X (t) at the output of the equivalence element 14.

The delta coder works as follows.

The results of the comparison by the comparator 1 of the input U (t) and the approximating U (t) voltage in the form of single or zero bits are written to the trigger 2 on the information input at the moments of arrival at its gate clock input of the frequency f J. from the clock input 27. Diff : 1the sequence Y (t) from the output of flip-flop 2 is the output signal, is the scrap of the encoder, and is simultaneously recorded in shift register 3 upon the arrival of the next clock pulses f to its gate input. Moving through the shift register 3, the pulse sequence Y (t) is analyzed by AND 4 and 5 elements and the OR 8 element, at the output of which short unit pulses B (t) are generated whenever a sequence of Y (t) appears two (or more) identical single or null characters, followed by another. Single pulse duration B (t) is determined by the duration of clock pulses f J,. The resulting shortening of the pulses B (t) is necessary for the normal operation of the first counter 0.

As is known, information about the frequency of the input signal can be obtained by analyzing the output sequence Y (t) on the number of changes in the sign of multi-element packs over a certain time interval T. Thus, the frequency range of the input signal U (t) with which the delta coder should work, can be divided into several frequency subbands and set the values for each of them

Nn

min of mtsi 1

VM

     min h- 1 MMM p

MO (KCC / IAIS1 Moncfv.iN

1X f

Each of the numbers N.

Min about

 corresponds to its frequency sub-band and (just as in the prototype) indicates that the encoder works with an excessively large quantization step, and therefore

low signal-to-noise ratio due to the high power of quantization noise and that the quantization step needs to be reduced by 4kkktoe of the numbers.

N.

(each of which

     - ALIX (1

set for your frequency

subband) indicates that the encoder is operating in the overload mode (the overload noise power is large) and that the quantization step g needs to be increased. Any number of pulses of the signal B (t) for the time T between

any of the pairs N

and N

will be

 “AMN i MIKK-I; ; testify that for

In this case, the encoder works with the optimal quantization step f and that it should not be changed yet.

The pulse counting function B (t) on the interval T is performed by the first counter 10, the counting input of which receives the sequence B (t). The periodic time interval on which the output sequence Y (t) is analyzed is determined by the number stored (in binary code) in block 13 and permanently present on the first group of conclusions of this block, and hence on the second group of inputs of the equivalence element 14. This number must be equal to the number of clock pulses placed in the interval TC. Thus, as soon as the second counter 11, to the counting input of which clocks are applied, reaches up to the number stored on the first output group of block 13, since the output of the equivalence element 14 has a single pulse X (t), which resets the counters 10 -12, having zeroed the first buffer register 22 and having entered the 6 and 7 elements as a control signal, marks the end of the previous and the beginning of the next analyzed interval Td of the output signal Y (t).

The pulse counting results B (t) by the first counter 10 are constantly analyzed by the decoder 16, which at the first output of the first group of outputs generates a short pulse C, 5 (t) to that element when the first counter 10 counts to N, 0 at the second output C ( t) at the moment when first counter 10 counts to

N

"By them

it.d, before the n-th output of the first

groups. In the same way short pulses of С 1.0 (t), ..., С ,, fc (t) to the image;

The outputs of the second group of the decoder 16, but at the same time the state of the first counter 10 is analyzed by NMO. . "" Xl results of analysis of the sequence of Y (t) and B (t) (signal

WITH

(t) and C, ft) ...

i, n the moment of their occurrence

recorded through the information inputs in register 22 and stored there until the end of the current analysis interval TD.

The analysis of the output sequence Y (t) on the number of changes in the sign of multi-element packs is performed using the 3 shift register, the And 4.5 elements. the second trigger 9 and the third counter 12. At the output of the element And 4 there appear short single impulses, when in the sequence Y (t) there are two or more single characters, the following ones, which, on the first input of the trigger 9, set it to unit The second input of the trigger 9 receives short single pulses from the output of the element And 5 at those moments when two or more zero symbols appear in the signal Y (t), followed by others. These pulses set the trigger 9 to the zero state.

Thus, the state of trigger 9 changes all the time when the sign of the packs changes. Counting the number of state changes of the trigger 9 during the time interval TC (performed by the third counter 12, to the counting input of which the direct output of the trigger 9 is connected. At the end of the analysis interval, the outputs of the third counter 12 generate (in binary form) the number of the frequency sub-band, which supplied to the control inputs of multiplexers 20 and 21.

The signals R (t), K ,, (t), ...,, ...,. (T), K (t) from the inverse outputs of the first n bits of the register 22 arrive at the information inputs of the multiplexer 20, and the signals K 7 о (t), ..., KI n (t) from the direct outputs of the second n bits of the register 22 arrive at the information inputs of the multiplexer 21. Thus, after the time interval T expires, the outputs of the multiplexers 20 and 21 turn off which pair of signals K,, (t) and li (t), the number i of which is allocated by the number formed at the outputs of the third counter 12.

The combination of signals from the outputs of the multiplexers 20 and 21 at the time of the end of the current interval T, goes through the elements 6 and 7 to the summing and subtracting inputs of the reversible counter 19.

If during the TO interval the number of pulses in the sequence B (t) at the output of the elements of OR 8 for some i-ro frequency subband is less than N, then the outputs of the multiplexers 20 and 21 are the signals M, (t) 1 and M, ( e) 0. Accordingly, at the subtractive input of the reversible counter 19 at the time of the end of the interval T, a single short pulse appears. If the number of impulses in the position B (t) is between N "and", then at the moment of the arrival of the next Impull X (t) there will be zeroes on both inputs of the reversible counter 19 and the reversible counter 19 will not change its state. If the number of pulses in the sequence B (t) during the time T "has reached the value N or exceeded it, then at the moment of the end of the analyzed interval T the summing impulse input of the reversing counter 19 appears a short single impulse.

Multiplexer unit 15 consists of several multiplexers with combined control inputs and separated information inputs. The information inputs of the block 15 multiplexers are supplied with a set of quantization steps ct, ... with which the device can operate and which are stored in block 13 as binary numbers. It is assumed that the binary number corresponding to cG is greater than the binary number corresponding to

.sg

cJ,,, etc., i.e.

; four

..v

When a short unit pulse arrives at the summing input of the reversible counter 19, the binary number at its outputs is increased by one unit and the next (larger) quantization step J from block 13 as a binary number is connected to the outputs of the multiplexer unit 15. If a single pulse arrives at the subtracting input of the reversible counting

19, then the previous (smaller) quantization step if quantized is connected to the outputs of block 15 multiplexers. The binary number corresponding to the current quantization step from the outputs of the multiplexer unit 15 is fed to the first group of inputs of the ALB 24 and, depending on the state of its control-.

input is either summed or subtracted from the binary number present on the second group of ALB 24 inputs and the result of a similar arithmetic operation

(produced in the previous clock interval), stored in buffer register 23 for one period of the clock sequence. The output of the buffer register 13 thus forms a binary number, the value of which determines the magnitude of the approximation voltage U (t) of the input signal in the encoder feedback circuit. The conversion of this binary number to the voltage level U (t) produces 1W1 25.

As follows from the description of the operation of a delta coder, its characteristic feature is the dependence of the values of the current N,

and N

from

 Pick 1 cuff of input parameters, and

the main factor influencing the use of a particular pair of H, and "; and NVMKC;, is the frequency of the input signal.

Thus, the quantization steps with which the encoder operates will be optimal for the entire frequency band of the spectrum of the transmitted speech signal, therefore the real band of the transmitted signals is greatly expanded.

Claims (1)

Invention Formula The delta coder containing the comparator, the first input of which is the information input of the delta coder, the output of the comparator is connected to the information input of the first trigger, the output of which is connected to the information input of the shift register, the control input of the arithmetic logic unit and the output of the delta -coders, direct and inverse outputs of the shift register bits are connected to the corresponding first inputs of the first and second AND elements, respectively, the outputs of which are connected to the inputs of the OR element whose output is connected En to the counting input of the first counter, the second counter, the outputs of which are connected to the first inputs of the equivalence element, the output of which is connected to the first inputs of the third and fourth elements AND and the zeroing inputs of the first buffer region and the first counter, the outputs of which are connected to the inputs of the first decoder the shots of which are connected to the information inputs of the first buffer register, the outputs of its third and fourth elements And are connected respectively to the subtracting and summing inputs of the reversible counter, the outputs to Then they are connected to the inputs of the second and third decoders and to the control inputs of the multiplexer unit, a permanent memory unit, the first and second outputs of which are connected respectively to the second inputs of the equivalence element and information inputs of the multiplexer unit, the outputs of which are connected to the first information inputs of the arithmetic unit. logic block whose outputs are connected to the information inputs of the second buffer register, whose outputs are connected to the second information inputs of the arithmetic logic unit and the inputs of the digital-analog converter, the output of which is connected to the second input of the comparator, the inverse outputs of the second and third decoders are connected to the second inputs of the third and fourth elements, respectively, the inputs of the synchronizer and the shift register and the first trigger, the counting input of the second counter, strobe the input of the second buffer register and the second inputs of the first and second elements I are combined and are clock inputs of the delta coder, characterized in that, in order to improve coding accuracy by expanding the frequency axes of the encoded signal, the first and second multiplexers, the third counter and the second trigger, the first and second inputs of which are connected to the outputs of the first and second elements, respectively, are entered into the delta coder; the output of the second trigger is connected to the counting input of the third counter; and the zeroing input of the second counter is combined and connected to the output of the equivalence element, the outputs of the third counter are connected to the control and digital inputs of the first and second multiplexers, the outputs of which are connected to the third odes respectively third and fourth members and the first and second outputs of the first buffer register are connected to respective data inputs of the first and second multiplexers. Phia.2