SU1374434A1 - Device for decoding binary codes in multiple repeat of message - Google Patents

Abstract

The invention relates to communication technology and can be used in systems of transmitting discrete messages with multiple repetitions. The aim of the invention is to improve the speed of the device. For this, the device contains a shift register 1, an AND 2 element, a delay element 3, a repetition counter 4, blocks 5 containing counters, keys, code comparison circuits, triggers, OR elements, an information input, clock inputs, a setup input, information outputs, an output end decoding device. 2 tab. 2 Il.

Description

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The invention relates to communication technology and can be used in systems of transmitting discrete messages with multiple repetitions.

The purpose of the invention is to increase the speed of the device.

Figure 1 presents the scheme of the device; Fig. 2 shows the spinning & processing unit.

The device contains a shift register 1, the element And 2, the element 3 delay, the counter 4 repetitions and blocks 5, containing counters 6, keys 7 and 8 comparison codecs, triggers 9, elements OR 10, information input 11, the first and second clock inputs 12 and 13, setup input 14, information outputs 15, output 16 of the decoding end of the device.

The device works as follows.

When the device is reset with the installation signal, the 4-repetition counter and the flip-flops 9 are set to the state O, and the number (n-m + +1) is recorded in the counter 6. After writing to register 1 the shift of the first repetition of the message signal

de message () information about the end of processing the entire message and bring the device

c In the initial state. Subsequently, when the information message O is received in this bit, the condition of coincidence of the numbers recorded in the counter for the 4 repetitions counter breaks .10 s, the signal at the output of the 8-comparison circuit disappears.

If the input of the counter 6 enters w 1 informational 1, it will overflow, at the output

15 of the counter 6, the Vits overflow signal of the counter 6 is received. The given signal, having arrived at the inverse control input 7, terminates the last one, which achieves the preservation of the signal

20 output of the counter 6, which is the informational output of the device, until the end of processing the entire message and resetting the device to its initial state.

25 When a signal appears at one of the inputs of the element OR 10, at its output, a signal is received indicating that the processing of the corresponding message bit has finished. With

The end of the repetition, which arrives at the input 30 by the appearance of signals at all the inputs 13, briefly opens the keys of the element I 2 at its output; Signal End Decoding appears. The decoding of the message ends.

7 and added one by one to the numbers, recorded in those counters 6, which are connected via keys 7 to the cells of the shift register 1, in which information data 1 are recorded. After a delay of pulse. The end of repetition is for the time required to complete the transients in counters 6, the unit is added to the number recorded in the 4 repetition counter. The device works in a similar way when processing subsequent repetitions.

Although not all repetitions were received and processed in the general case. The output signal b corresponds to the value 1 of the corresponding bit of the decoded message.

The operation of the device or the JBStudio 40 tab. 1 and 2 using the example of decoding one bit of a message for cases of the status of a decoded bit O and 1, respectively. The device implements the bitwise rule

In comparison schemes 8, 45 out of 7 are decoded. In the columns

de message () information about the end of processing the entire message and bring the device

In the initial state. Further, when the information message O is received in this bit, the condition of coincidence of the numbers recorded in the counter of the 4 repetition counter is violated, the signal at the output of the 8-comparison circuit disappears.

If the input of the counter 6 enters w 1 informational 1, it will overflow, at the output

the counter 6, the VITS overflow signal of the counter 6. The given signal, having arrived at the inverse control input 7, terminates the last one, which achieves the preservation of the signal on

the output of the counter 6, which is the informational output of the device, until the end of processing the entire message and bringing the device to the initial state.

When a signal appears at one of the inputs of the element OR 10, at its output a signal indicates that the processing of the corresponding message bit has finished. With

although in general, this case has not received and processed all its repetitions. The output signal b corresponds to the value 1 of the corresponding bit of the decoded message.

The operation of the device or the JBt. 1 and 2 using the example of decoding one bit of a message for cases of the status of a decoded bit O and 1, respectively. The device implements the bitwise rule

Comparison of numbers recorded in counters biv counter 4 repetitions. The output signal of the comparison circuit 8 appears in the case of equality of these numbers, which indicates that in the corresponding discharge of the message in the repetitions of received (p-mon-1) informational O, so it cannot be accepted m 1, since (pt + 1). The signal at the output of the comparison circuit 8 transfers the trigger 9 to the state 1. The trigger 9 is inserted into the device for storing the reception fact in the corresponding tables the repetition bits are shown, as well as successively in time varying states of the counters 6 and 4. The symbol is marked moments at which the decision is taken to end the docking of this bit of the message.

Table 1

B1

code comparison blocks, the group of elements SH, element I and the delay element whose input is combined with the first control inputs of the group keys and is the second clock input of the device, the output of the delay element is connected to the counter input of the counter, the outputs of which are connected to the corresponding first inputs of the device Comparison of group codes, the second inputs of which are connected to the outputs of the corresponding group counters, and the outputs - to the single inputs of the corresponding group triggers, the outputs of the group triggers are connected to the first

15

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the inputs of the corresponding elements OR groups, the overflow outputs of the counters are connected to the inverse control inputs of the corresponding group keys and the second inputs of the corresponding OR elements and are information outputs of the device, the outputs of the OR elements of the group are connected to the corresponding inputs of the AND element whose output is the ending output the decoding device, the setup inputs of the counter, the group counters and the zero inputs of the group triggers are combined and are the installation input of the device.

Claims (1)

Claim A device for decoding binary codes for repeated repetition of a message containing a shift register, the information input of which is the information * input of the device, a clock input is the first clock input of the device, the outputs of the bits of the shift register are connected to the inputs of the corresponding group keys, the outputs of which are connected to the inputs of the corresponding group counters, a counter, a group of triggers, characterized in that, in order to improve the performance of the device, a group of code comparison blocks, a group of NT OR, element AND and a delay element, the input of which is combined with the first control inputs of the $ keys of the group and is the second clock input of the device, the output of the delay element is connected to the counter input of the counter, the outputs of which are connected to the corresponding first inputs of the group code comparison blocks, the second inputs of which are connected to the outputs of the respective counters of the group, and the outputs are connected to the single inputs of the corresponding triggers of the group, the outputs of 15 triggers of the group are connected to the first inputs of the corresponding elements of the OR group, the overflow outputs of the counters are connected to the inverse control inputs of the corresponding group keys and the second inputs of the corresponding OR elements of the group and are information outputs of the device, the outputs of the OR elements of the group are connected to the corresponding inputs of the AND element, the output of which is the output of the end of the decoding of the device, the setting inputs of the counter, the group counters and the zero inputs of the group triggers are combined and are the installation input of the device.