SU1367030A1 - Device for checking response actions of operator - Google Patents

Abstract

The invention relates to a technique for measuring and training the psycho-physiological qualities of an operator and can be used during training, selection and operational control of the activities of operators. The purpose of the invention is to increase the accuracy of the device for classifying the response of the operator upon presentation of an incompletely filled stimulus field. The essence of the invention is to make it possible to provide errors both in the type of wrong choice of the sign and in the error of the wrong location of the sign in the field of the information array. The device contains reHepatop 1, block 2 of response memories, block 3 of the pattern memory, block 4 of keys, element OR 5, block 6 of comparison, element OR 7, block 8 of error analysis consisting of AND 9, .10 elements, inverter 11 , the element And 12, the inverter 13, the element And 14, the inverter 15. 1 Il. Q (L CZ

Description

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The invention relates to training equipment, in particular, to a training technique and an assessment of the development of professional skills and professionally important qualities of operators, and allows classifying operator errors as the wrong type of character, as well as type errors incorrectly 7030

2

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the presence of a response) or the need to answer with elements 5 and 7, respectively. Block 8 functions as follows. In the presence of a high level signal at the outputs of block 6 and element 5, the output of element 9 produces a high level signal, which corresponds to the correct response

Placement of the sign in the information Q of the operator in the right place information field. The device can be used in the visual memory simulator with incomplete filling of the information array of stimuli or in the innational array. In the presence of a low level signal at the output of block 6 at the output of the inverter 11, a high level signal is generated and enters

20

25

formation systems for blocking 15 to the input of element 10. If this is the case when the records of edited information arrays are in violation by the operator of the area of the array to which it is admitted.

The purpose of the invention is to improve the accuracy of the device by highlighting errors both of the type of wrong choice of the sign and of the type of wrong location of the sign in the field of the information array.

The drawing schematically shows a device for monitoring operator response,

The device contains a g-generator 1 of the sequence of codes (pulse train) block 2 of response memories, block 3 of the memory of response standards, block 4 of keys, element 5 OR, block 6 of comparison (responses) element OR 7, block 8 of error analysis, elements AND 9,10, the inverter 11, the element And 12, the inverter 13, the element And 14, the inverter 15.

The device operates as follows.

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Elements 5 and 7 receive high level signals to the first and second inputs of element 10, respectively, then a high level signal is generated at its output, which corresponds to an incorrect response of the operator at the right place in the information array. If there is a low level signal, element 5 at the output of the inverter 13 the signal is high and arrives at the input of element 12. If element 7 is supplied with a high level signal at the input of element 12, a high level signal is formed at its output, which corresponds to. lack of response from the operator in the right place of the information array. If a low level signal is present in element 7, a high level signal is generated at the output of inverter 15 and is fed to the input of element 14, then a high level signal is formed at its output, which corresponds to the presence of a response.

After installation in the initial state - 40 where it was not provided. Description

The generator 1 is generated the read address for blocks 2 and 3. As a result, the response codes and the response standard are generated, respectively. On tires from block 2, the response code goes to block 6 and item 5. On tires of block 3, the response standard code goes to block 6 and item 7.

At the same time, block 5 performs code compaction and generates a high-level signal when the codes match. At the outputs of elements 5 and 7, high level signals are formed if at least one input is present

high level signal From the output of the gg all memory addresses.

ka 6 the signal arrives at the input of the block. In the same way, the device pea8, to which signals are received, emits the indicated purpose of the invention

Whose level (or signals of a low division are wrong in this case if there is no signal filling in the information Mayan array. If there is a low signal, the output of block 6 at the output of the inverter 11 generates a high signal and receives

to the input element 10. If at the same time

Elements 5 and 7 receive high-level signals to the first and second inputs of element 10, respectively, then a high-level signal is generated at its output, which corresponds to an incorrect response of the operator at the right place in the information array. If there is a low level signal on element 5, a high level signal is generated at the output of the inverter 13 and is fed to the input of element 12. If a high level signal from element 7 is received from element 7, then a high level signal is generated at its output, which corresponds to it. lack of response from the operator in the right place of the information array. If a low level signal is present in element 7, a high level signal is generated at the output of inverter 15 and is fed to the input of element 14, then a high level signal is generated at its output, which corresponds to the presence of a response.

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all other combinations of signals and the corresponding states of element 9 are similar. The signals from the outputs of elements 9, 10, 12, 14, 5 and 7 are fed to the control inputs of block 4, and the pulse from the output of generator 1 goes to the inputs of the keys of block 4 and if there is a high level at the input of the key of block 4, the pulse passes Q for further processing. After

This generator 1 generates the next address in blocks 2 and 3, and the operation of the device is repeated until it is viewed.

Siva from sign installation errors in the free space of the information array. A device can work as a blocking device to write an information array to an information system if its arrays are filled with different operators at the access indicated by them, and an access mask is used as the response standard.

Claims (1)

Invention Formula An operator response control device containing a response memory block, whose information input is the input of the device responses, and the output is connected to the first input of the comparison block, the second input of which is connected to the output of the standard memory, error analysis block and key block, outputs which are the corresponding outputs of the device, characterized in that, in order to improve the accuracy of the device, the code sequence generator, the first and second OR elements are entered into it, and the error analysis block contains first, second and third inverters, first, second, third and fourth AND gates, the outputs of which are connected respectively to the first, second, third and 367030 The fourth information inputs of the key block, the fifth and sixth inputs of which are connected to the outputs of the first and second elements OR, respectively, connected to the inputs of the first and third inverters, respectively, the outputs of which are connected to the first inputs of the third Q th and fourth elements, respectively, the second inputs of which connected to the outputs of the second and first elements OR, respectively, connected to the first inputs of the second and first elements AND, respectively; the second input of the first element AND is connected to the output of the block with avneni connected to the input of the second inverter, whose output is connected to the input of the second vtorsh ele20 ment And, the third input of which is connected to the output of the first OR gate, the inputs of the first OR element connected to the corresponding memory block outputs the responses, the inputs of the second element 25 OR are connected to the corresponding outputs of the memory of standards, the address inputs of the memory and standards are connected to the information output of the code sequence generator, 30, the sync output of which is connected to the control input of the key block, and the setup input and the start input are the corresponding inputs of the device.