SU1365107A1 - Information compression device - Google Patents

Abstract

The invention relates to the field of measurement and computational tech nics of NICKY and can be used in devices for collecting, converting, transmitting and automating the processing of electrical signals. The aim of the invention is to increase the accuracy of the information compression device with non-stationary input signals. The goal is achieved by introducing a controlled frequency divider, Y element and new connections, and in accordance with the determined sampling frequency, the division ratio of the controlled frequency divider changes, depending on which the recording frequency of the significant ordinates of the processed signal changes into the output buffer memory . 3 il.

Description

65

cl

computer technology and can be used in devices for collecting, converting the transmission and automated processing of electrical signals.

The aim of the invention is to improve the accuracy of the compression device.

the device in the initial state from the frequency grid at the output of the frequency divider 4 allows you to transfer the highest frequency to the input of register 7, i.e. fHC Under this adder state, the division ratio of the controlled divider 8 is the same as the information divider with non-stationary input IQ 3, i.e. the recording of the ordinates in the second block of signals 9 of the buffer memory is carried out with

the device in the initial state from the frequency grid at the output of the frequency divider 4 allows you to transfer the highest frequency to the input of register 7, i.e. fHC Under this condition, the amount

the start frequency of the A / D converter 1. In parallel, the signal ordinates are recorded in the first block 10 of the buffer memory. 15 signal overflow counter 11, the volume of which is equal to the specified number

and shift register with S, „S ,, 0. The words recorded in the first block 10 of the device (Fig. 1) contain a buffer memory, switch ACPP 1, generator 2 of pulses, first ger 12, and keys 14 and 15 open.

3 and second 4 frequency dividers, comm-20 At the same time, trigger signal 12 posator 5, adder 6, register 7 shifts to the second input of the element And and

FIG. 1 shows a functional diagram of the device; in fig. 2 - sync pulses at the outputs of the elements of the device in FIG. 3 - signals at the outputs of the first buffer memory block

ha, controlled frequency divider 8, second 9 and first 10 blocks of buffer memory, counter 11, trigger 12, element 13, keys 14-16, subtractor 17. quad 18, averager 19, comparison block 20 and block 21 constant memory

The device works as follows.

When the device is turned on, its block is reset, in which the blocks 9-10 of the buffer memory, the counter 11 and the adder 6 are cleared, the trigger 12 is in such a state that the keys 14-16 are closed.

Analog input signal is digitized to ADC 1, hour

In order to compress the ordinates 30, the differences between the previous and the subsequent significant ordinates are determined. To determine these differences, in the first averaging cycle, the shift register 7 from switch 5 is supplied with a twice lower frequency relative to the data output rate from the first buffer memory unit 10. Consequently, in the shift register 7 from the first block of buffer memory, the start-up powering of which is formed by dividing by a constant value the codes of every second ordinator of the 2 pulses in the signal dividers. These codes are given on le 3 frequencies. The output frequency and the second input of the subtractor 17, on the first pulse f, of the generator 2 pulses, the input of which receives the codes of all is chosen much greater than the ordinate of the signal. The differences between the start frequency of the ADC 1 f, which is 45 Dzmi ordinates from subtractor 17, are selected such as, for example, two d squares per square 18 and are larger than the maximum possible frequency of the spectrum are integrated into the averager 19. The output the average 19 is the actual value of the rms input signal fg (figa).

integrated into the average 19. The real average RMS obtained at the output of the average 19

The pulse sequence with the frequency error Qc from the compression of the instant repetition f from the output of the generation a is compared in the block of the torus 2 pulses also goes to the input of the divider 4 frequency, the output of which forms the hell of the pulse sequences, the repetition frequency g - S, which form a grid of frequencies (Fig. 2S). These pulses are a sequence-summing input of the adder 6 signal, and are fed to the inputs of the switch 5. The adder 6, which controls the comm20, compares with 7; these errors 5 ,,; (, c,, c, d, stored in 21 constant memory

2 g 1: About

block 2

(S, VHH block

vaKc) P 3 comparison missions transmit via key 14 to

which increases the contents of the sum of the torus by one and switches the output

after the last ordinate is recorded in block 10 of the buffer memory at the output of the element I, a signal is generated that opens the key 16. From this moment begins the compression of the coordinates filled in block 10 of the buffer memory with a high

clock frequency f

gi

In order to compress the ordinates, the differences between the previous and the subsequent significant ordinates are determined. To determine these differences, in the first averaging cycle, the shift register 7 from switch 5 is supplied with a twice lower frequency relative to the data output rate from the first buffer memory unit 10. Consequently, the codes of every second signal ordinate are written to the shift register 7 from the first block of the buffer memory. These codes are fed to the second input of the subtractor 17, the first input of which receives the codes of all the ordinates of the signal. The differences between the co-Dzmi ordinates from the subtractor 17, the square of the square in the square 18 and

Codes of every second signal ordinates. These codes are fed to the second input of the subtractor 17, the first input of which receives the codes of all the ordinates of the signal. The differences between the co-Dzmi ordinates from the subtractor 17, the square of the square in the square 18 and

integrated into the average 19. The actual value of the mean square error obtained from the output of the average 19 is compressed in information and compared to the block - S, the summing signal of the adder 6

20 comparisons with 7; these errors 5 ,,; (, c,, c, d, with 21 memorials stored

2 g 1: About

block 2

(S, VHH block

vaKc) P 3 comparison missions transmit via key 14 to

tic error due to compression of information and is compared in the block - S, the summing input of the adder 6 signal

which increases the content of the adder by one and switches the output

31

switch to a lower frequency coming from the second divider 4 frequency. This ends the first averaging cycle and starts the next cycle. In the next cycle, a lower frequency allows, for example, halving the number of ordinate codes recorded in register 7. At the same time, the output frequency of ordinate codes from the buffer memory block 10 is kept much higher than in the previous cycle. start up ADC 1 f. The volume of the first buffer memory unit 10 determines the averaging interval of the averager 19. The averaging interval is proportional to the magnitude of the correlation interval of the input signal and inversely proportional to the predetermined error due to signal compression.

The averaging cycles of the squares of differences, obtained with increasing step, follow each other.

 2 2

another until S i mn, if the condition is 5, „„ S

Mqfcc (Figs. Za, b) the signal comparison unit does not produce and the state of the adder 6 does not change. Subject S

s

 from the output of the unit, compared with the switch 15, to the subtracting input of the adder 6, a signal is supplied that reduces the contents of the adder 6 and, therefore, the frequency of the pulses switched from the output of the second frequency divider to the control input of the shift register 7 increases. After several cycles of averaging at the output of switch 5, such a pulse frequency is set at which min 3 mA s. Corresponding to this frequency, the state of adder 6 sets the required dividing ratio of the controlled frequency divider, which generates the sync pulses of recording significant ordinates in the second block 9 of the buffer memory, i.e. The determination of the required sampling frequency is carried out at high speed in 1 / G time, and the essential samples of the input signal are recorded in the second block 9 of the buffer memory in real time. After the arrival of the next count with ADC 1, its value is recorded in the first block 10 of the buffer memory, with the first recorded in block 10, the value of the ordinate is erased. Then, the described processing is again carried out.

five

five

About Q with

five

07

The first block 10 of the buffer array. If the condition ,,,,, is not satisfied, the contents of the adder 6 are changed in the right direction and, therefore, the division factor of the frequency divider 8 is changed.

Thus, the sampling frequency of the signals to be transmitted adaptively changes as the frequency properties and dispersion of the input signals change.

Claims (1)

Invention Formula A device for compressing information containing an analog-to-digital converter, whose input is the input of the device, a pulse generator, the output of the pulse generator is connected to the input of the first frequency divider, the output of which is connected to the control input of the analog-digital converter, and the trigger the output of which is connected to the control inputs of the first and second keys, the output of the analog-digital converter is connected to the input of the first block of the buffer memory, the shift register, the output of which is connected to the first the subtractor input, the second input of which is combined with the shift register input, the output of the subtractor is connected to the quad input, the quad output is connected to the input of the averager, the output of which is connected to the first input of the comparison unit, the second and the second memory input connected to the second input the outputs of the comparison unit are connected respectively to the second inputs of the first and second keys, the output of the first key is connected to the summing input of the adder, the output of the second key is connected to the subtractive input of the adder, the output of which connected to the control input of the switch, the information inputs of which are connected to the corresponding outputs of the second frequency divider, the output of the switch connected to the control input of the shift register, the output of the second buffer memory block is the output of the iCTsa device, the third key, characterized in that in order to improve the accuracy of the device with non-stationary input signals, a controlled divider is introduced into it 51 frequency and element And, the output of the adder is connected to the control input of the controlled frequency divider, the output of the first frequency divider is connected to the first input of the element And to the input of the controlled frequency divider, the output of which is connected to the control input of the second block of the buffer memory, the trigger output is connected to the second input of the AND element, the output of which is connected to the control input of the third Fzg.1 651076 the key, the output of which is connected to the control input of the first block of buffer memory, the output of the pulse generator is connected to the inputs of the third key and the second frequency divider, the output of the first block of buffer memory is connected to the input of the shift register, the output of the counter is connected to the trigger input, 10 the output of the analog-digital converter is connected to the input of the second block of buffer memory. but N 5 | | 1  "S five | § | h § I I I I I t time shave 8peAfjt ut. z: 5l ii i §I  V 1 c Illllllllllllllllllllllllllllllllllll Si L a III MM II III Srig.Z epewi