SU1363142A1 - Relay system test-control device - Google Patents

Abstract

The invention relates to automation and computer technology and to the brainworm to be used for test control of the performance of relay systems, such as temperature and humidity control systems in industrial premises. The purpose of the invention is to improve the speed of the device by adapting to the duration of the testing of test commands by the relay system. The device contains a start-up unit 1, a pulse former 2, a switch 3, a HE element 4, an AND 5 element a distributor of 6 pulses, a test command unit 7. A comparison unit 8, a delay element 9, a decoder 11, an indication unit 12, 1 Il. sg

Description

 The invention relates to automation and computer technology and can be used to test the performance of relay systems, such as temperature and humidity control systems in industrial premises.

The aim of the invention is to increase the speed of the device by providing adaptation to the duration of the testing of test commands by the relay system.

The drawing shows a functional diagram of the device.

The device contains a start-up block I, a pulse driver 2, a switch 3, a HE 4 element, an AND 5 element, a pulse distributor 6, a test command block 7, a comparison block 8, a second delay element 9, a first delay element 10, a decoder 11 executed on the elements And 11.1-I1.p according to the number of clock cycles of the control unit 12 of the display, including the display elements 12.1-12.P + 1, the driver 2 pulses, having counting installation and gate inputs 1 14 and 15, respectively, and containing a counting trigger 16, elements And 17 and 18, elements NOT 19 and 20 and first and

second exits 21 and 22.

The controlled linear system 23 is connected by an input and output to the third outputs and the second information inputs of the switch 3.

The distributor 6 pulses are made with two clock tires connected respectively to the outputs 21 and 22 form 2 pulses.

The outputs of the distributor 6 are formed by normally open contacts of clock relays (not shown).

The device works as follows.

The test control mode of the relay control system 23 is inputted by the start-up unit 1, the output of which is fed to the setup input 14 of the driver 2 pulses and sets the counting trigger 16 to the initial position at the R input, resulting in a single signal to the first input of the element 18. At the same time, the output signal of the startup block 1 is supplied to the control input by the switch 3, which is switched off by this command

five

0

five

0

five

0

five

0

five

The system 23 from the control object (not shown) and connects its inputs to the output of the test command unit 7, and its output to the input of the comparison unit 8. Such switching is carried out through the first and second information inputs and the first and third outputs of the switch 3. The feedback signal with the report about switching the system 23 to the test control mode comes from the second output of the switch 3 through the gate input 15 of the driver 2 pulses to the second inputs of the elements Both 17 and 18 and to the first input of the element And 5. As a result, the output of the element And 18 forms a zero signal, which through the element NOT 20 comes in the form of a single signal to the output 21 and further distribute to the first clock bus 6. Distributor 6 generates the output signal of the first control cycle for block 7, which, in accordance with a given test control program, inputs the first test command into the system 23. At the output of the comparison unit 8 at this time there is a single signal Inequality, which, through the NOT 4 element, starts up the first delay element 10. The magnitude of the maximum time delay of element 10 is chosen to be obviously the largest test control control longest in terms of the tact duration.

System 23, reacting in accordance with a predetermined control algorithm to the incoming from block 7

The test command, which generates signals of control actions at its output, which through the second information input and the first output of switch 3 arrive at block 8 of comparison. When these signals coincide with the signals programmed for this control cycle, block 8 generates a zero Equivalence signal, which is NOT sent through the element 4 as a single signal to the input of the And 5 element. Since there are single signals at both And 5 element inputs, then its output produces a zero signal that triggers the second delay element 9. After the delay element 9 is triggered, its output signal is fed to the counting input 13 of the driver 2, which leads to the transition of the trigger 16

to the opposite state and to the opposite of its output signals. As a result, the output signals of the AND elements 17 and 18, the HE elements 19 and 20, and the former 2, whose output 22 has a single signal and the output 21, zero, change to opposite values. This causes the formation of the signal of the second clock cycle by the distributor 6 for the test command block 7, which introduces a new command into the system 23. The minimum delay time of the second element 9 should overlap the time interval during which all logic elements of the controlled system 23 are switched after being removed from it outputs by block & the signals that form the final Equivalence signal, i.e. the minimum time delay must be greater than the transition time of switching logic elements, which takes place after the completion of the previous test command before entering the next one. Otherwise, the input of a new test command can be superimposed in time with a transient state of the logic elements and the result of the control will be false.

After working out the second test command, a third is entered, and so on. At the end of the test control, that is, after working out the last test command n, the distributor 6 generates a service (n + 1) -th cycle affecting the start block 1, which outputs the system through switch 3 23 from the test control mode, connecting its inputs and outputs to the control object.

If the testing time of a test command exceeds the maximum hold time, then the first delay element 10 will be triggered, the output of which at the first input of block 12 lights up a common banner Fault. At the same time, the output signal of the element 10 through the first input of the decoder 11 acts on the first inputs of the elements 11.1 and 11, p, the second inputs of which are affected by the signal TeVNIIPI

Order 6361/37 Circulation 863

. Prod-polygr. pr-tie, Uzhgorod, st. Project, 4

kuschego tact test control. This leads to triggered1) The chassis corresponding to this clock cycle of the element I, whose output signal from the second outputs of the decoder 11 goes to the corresponding second input of the display unit 1.2 and lights one of the display elements 12 ,, ... the display of this block corresponding to test team number; on which the fault was received.

Claims (1)

Invention Formula 0 five 0 five 0 0 five A test control device for relay systems containing a pulse distributor connected by the first outputs to the inputs of the test command block, a comparison block, a start block, a first delay element, a display block, which differs from the fact that, in order to improve speed, the decoder, the switch, the pulse shaper, the element AND, the second delay element and the element NOT connected by the input to the output of the comparison unit, and the output to the first input of the AND element and through the first delay element to the first inputs of the display unit the second input is connected to the first outputs of the pulse distributor and the first inputs of the comparison unit connected by the second inputs to the first outputs of the switch connected by the first information inputs to the outputs of the test command block controlling the input the start-up output. and the installation input of the pulse former, and the second OUTPUT - with gating input g of the pulse former and the second input of the element I connected via the output of the second delay element to the counting input of the pulse generator connected with the first and second outputs to the first and second clock inputs of the pulse distributor connected with the second output to the input of the trigger unit, the third outputs and the second information inputs of the switch are control inputs and outputs of the device. Subscription