SU1356250A1 - Device for recurrent phase start - Google Patents

Abstract

The invention relates to communication technology. The purpose of the invention is to improve the noise immunity, the device contains a switch 1 mode of operation, a recurrent shift register (PPC) 2, an adder 3 modulo two, a decoder 4, a counter of zeros 5, a counter of 6 intervals, a threshold unit 7, the element OR 8, the element . And 9. To achieve the goal, a code comparison block 13 is entered, a NOT element 14, a decisive block 15, a count of the number of confirmations of the capture 16 and an additional recurrent shift register 10, two elements 11 and 12, an OR element 17. The device operates in the search mode and in the mode of statistical processing. I il. 00 JV O) ate

Description

The invention relates to communication technology and can be used for robust recurrent phase start in session communication systems.

The purpose of the invention is higher noise immunity.

The drawing shows a structural electrical circuit of a recurrent phase start device,; Device for recurrent phase start Contains switch 1: operating mode, recurrent register 2 shifts, modulo-3 adder two, decoder 4, counter 5 zeros, counter 6 intervals, threshold unit 7, element OR 8, element 9, additional shift recurrent register 10 shift , the first and second additional elements And 11 and 12, block 13 comparison of codes, the element NOT 14, the decisive block 15, the counter 16 the number of confirmations of the capture, the additional element OR 17.

The device is a recurrent phase start works as follows

The returns of the recurrent code received from the communication channel through switch 1, the initial state of which corresponds to the search mode, are fed to the input of the recurrent shift register 2 and the adder 3, to the other input of which a signal is received from the output of the recurrent register

2 shift. In the case of receiving a recurrent sequence with a code structure generated by a recurrent shift register 2 with closed feedback, at the output of the adder

3po is a sequence of zeros, the count of which is counted by 5 zeros, which is reset to zero with each mismatch.

Upon receipt of the additional M pulses coinciding with the output of the counter 5 zeros, a signal is received at the input of switch I, through which the latter is switched to the statistical processing mode, while the feedback loop of the recurrent shift register 2 closes and it starts to work independently. The same signal from the output of the counter 5 zeros through the open permitting potential from the output of the element NOT 14 the second additional element I 12 rewrites the contents of the recurrent shift register 2 into the additional recurrent

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Shift register 10, which from this point in time begins to work in phase with recurrent register 2, and the signal from the output of the second additional element I 12 also performs through the additional IL 17 element the counter 16 clears the number of capture confirmations. the statistical processing mode, the signal from the output of the counter 5 zeros, makes a census of the state of the first group of conclusions of the decision block 1 5 into the counter of 6 intervals with its subsequent launch, the latter in turn the signal arriving at the first input of the threshold block 7 also fixes the state of the second group of conclusions of the decision block 15 in the threshold block 7 and starts it.

The state of the first and second groups of outputs of the decision block 15 depends on the state of the recurrent shift register 2 at the moment of the last transfer to the autonomous generation of the recurrent sequence, i.e., on the number of codd elements enclosed between the last Mth symbol of the undistorted package and phase start, At the same time, the work of the decision block 15 is made dependent on the number of previously recorded undistorted plots in case of negative results of statistical processing, preceded by oh recursion in the current period, the rental sequence that displays th state counter 16, the number of capture confirmations

When the device enters the statistical processing mode, the 6 interval counter forms a valid inter N shaft of length N, during which the threshold block 7 counts the mismatch signals of the received code with the elements generated by the recurrent shift register 2.

Q length. If at the moment when the end of the valid interval signal comes from the output of the counter 6, the threshold unit 7 detects the number of mismatches L less than the allowed one, then the signal from the second output of the threshold unit 7 will go to the control input of the relay of the operating mode switch 1, standby phase start5

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ka, as evidenced by the resolving potential at its second output. In this case, the signal from the output of the decoder 4, which is configured to the combination of the phase start, through the open element And 9 enters the output of the device.

When the number of errors L in the valid interval is more than acceptable, the signal from the first output of the threshold block 7 sequence OR element 8 will reset the device, put the switch 1 into the search mode and reset the counter to 5 zeros. When, in the search mode, the newly zero uninterrupted interval of length M is detected by the zero counter, the device will go into statistical processing mode, and the initial state of the interval counter 6 and the threshold block 7 will be determined by whether the recorded M matches are related to the previously analyzed recurrent cycle. sequence or not. The fact that the undistorted interval of the recurrent sequence is found in the previously considered recurrent cycle is determined by the block. 13 comparisons of codes that produce an indication of the identity of the states of the recurrent shift register 2 and the additional recurrent shift register 10 at the moment the signal from the output of the counter 5 zeros arrive. During the common mode of the recurrent shift registers 2 and 10, there is a potential , and at the second input of the second additional element And 12 - the inhibitory potential for the signal from the output of the counter 5 zeros, while the signal from the output of the first additional element And 11 increment It counts the contents of the counter 16, the number of confirmations of the capture, in this case, the length of the valid interval and the allowable mismatch threshold are significantly reduced. If the undistorted portion of the recurrent sequence is related to a subsequent recurrence cycle that has not yet participated in the analysis, as evidenced by the non-phase operation of the recurrent shift register 2 and the additional recurrent shift register 10 low potential at the output of block 13 comparison of codes

And 11 is blocked, and at the second input of the second additional element 12, the resolving potential is established. In this case, with the arrival of the signal from the output of the counter 5 zeros, announcing the capture of the undistorted portion of the recurrence, the counter is reset to 16, the number of confirmations of the capture and the state of the recurrent shift register 2 is rewritten into an additional recurrent shift register 10, i.e. it is phased. In this case, the supporting unit 15 places the maximum codes on the first and second groups of its outputs.

A general reset of the device occurs each time with a signal from the output of the decoder 4 of the controller; in addition to transferring the operation mode switch 1 to the search mode and zeroing the counter 5 zeros, the counter 16 of the number of capture confirmations is reset.

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Claims (1)

Formula of the invention n. A recurrent phase start device containing sequentially connected operating mode switch, recurrent shift register, modulo-two adder, counter of zeros, interval counter, threshold block and OR element, and also the output of the recurrent shift register bits through the decoder is connected to the first input of the AND element and the second input of the OR element, the output of which is sub-keyed to the installation inputs of the zero counter and the operation mode switch, the other output of which is connected to the second input AND gate whose output is output ustroystg va, to first and second inputs of the control mode switch connected sootvetstvennd another threshold output unit and the zeros counter output, first data input  combiner mode switch It is connected to the second input of the modulo-two adder and is the input of the device, the output of the recurrent shift register is connected to the second information input of the operating mode switch, and the information input of the zero counter is connected to the second input of the threshold block, which is different in that it is aimed 5 nor noise immunity, an additional recurrent shift register, a code comparison unit, the first and second additional AND elements, the NOT element, the count of the number of confirmations of the capture, the additional OR element, and the decisive block are entered, while the bits of the main recurrent shift register are connected to the corresponding inputs of the additional recurrent shift register, the decision block and the code comparison block, to the other inputs of which the corresponding outputs of the additional recursion register are connected shift, and the output of the block comparing the codes is connected to the first input of the first additional element AND and the input of the element NOT whose output 20 is connected to the first input of the second additional element AND, to the second 13562506 the input of which and the second input of the first additional element I is connected to the output of the zero counter, the output of the first additional element I) is connected to the counting input of the counter for the number of capture confirmations, the outputs of the bits of which are connected to the corresponding inputs of the decision block, the outputs of which are connected to the corresponding inputs of the interval counter and the threshold block output buto- Additional element AND is connected to the input of the record of the additional recurrent shift register and the first input of the additional element OR, to the second input of which the output of the decoder is connected, and the output of the additional element OR is connected to the zeroing input, the counter of the number of capture confirmations. Editor M. Andrushenko Compiled by P.Kurchev Tehred M.Hodanich Order 5814/56 - Circulation 636 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader L. Pilipenko