SU1159172A2 - Start-stop demodulator - Google Patents

Abstract

1. START-UP DEPLOYER according to auth.St. No. 4.97741, which means that, with a speed increase when operating in a channel with free access, a sequentially connected decoder and an additional element I, a are entered into the demodulator also an OR element, with the OR element connected between the first additional output of the synchronization unit and the additional stop input of the start-stop trigger, the input of the decoder and the output of the supplementary element H are connected respectively to the second additional output of the synchronization unit and to the second input of the element OR, and the second input of the additional element AND is connected to the output of the multi-input coincidence block. 2. A demodulator according to claim 1, I, which is based on the fact that the synchronization unit contains a series-connected pulse counter and a first decoder, as well as a second decoder, the input of which is connected to the output of the pulse counter, and with S the counting and outgoing inputs the counter (L pulses are respectively the first and second inputs of the synchronization unit, and the outputs of the first and second decoders and the output of the pulse counter are respectively the output, the first auxiliary output and the second auxiliary output of the synchronization unit.

Description

1 The invention relates to telecommunications and can be used for start-stop demodulation of information blocks. According to the main author. St. (| 497741 known start-stop demodulator containing sequentially connected address clock detector, start-stop trigger, element .A, synchronization unit and decision unit with sign detectors connected to it, as well as a reference frequency generator connected to the second input of the AND element , the outputs of the sign markers are additionally connected via inverters to the multi-input block of coincidence, the output is through a series of connected character counters and logic thresholds, the block is connected to the stop input of the hundred a stop trigger, the controlling and tilting inputs of the character counters are connected respectively to the start and stop outputs of the start trigger, and the output of the synchronization unit is additionally connected to one of the inputs of the multiple input matching unit OJ. A disadvantage of the known start / stop demodulator is the low speed during operation free access channel. The purpose of the invention is to increase the speed of operation when working in a free access channel. . The goal is achieved by the fact that a start-stop demodulator containing a sequentially-connected address clock detector, a start-stop trigger, an AND block of the synchronization unit and a decision block with sign detectors connected to it, and a reference frequency generator connected to the second input of the And element, detectors outputs the characters are additionally connected via inverters to a multi-pass coincident unit, the output of which is connected through a sequentially included character counter and logical threshold unit To the stop input of the start / stop trigger, the control and reset output of the character counter are connected respectively to the start and stop outputs of the start stop. Trigger, and the output of the synchronization unit is additionally connected to one of the inputs of the multiple input matching unit, the connected decoder and additional element are entered And, as well as the OR element, while the OR element is included between the first additional output of the synchronization unit and the additional stop input of the start-stop trigger, the input eshifratora and yield additional AND gate connected respectively to the second additional output of the synchronization unit and the second input E, ementa OR, and the second input of the complementary element and connected to the output multi-input block matcher. The synchronization unit contains a serially connected pulse counter and a first decoder, as well as a second decoder, the input of which is connected to the output of the pulse counter, and the counting and zeroing inputs of the pulse counter are the first and second inputs of the synchronization unit, respectively, and the outputs of the first and second decoders and output pulse counters are an output, a first auxiliary output, and a second auxiliary output of a synchronization unit, respectively. The drawing shows a structural electrical circuit of a start-stop demodulator, a start-stop demodulator contains a 1 address-clock signal detector, a start-stop trigger 2, an IZ element, a synchronization unit 4, a decisive unit 5, a multi-input unit 6 coincidence, inverters 7-9, detectors of 10-12 characters , the generator 13 of the reference frequency, a counter of 14 characters, a logic block threshold 15, a decoder 16, an additional element AND 17, an element OR 18. The start-stop demodulator works as follows. The address clock signal from the detector 1 through the start-stop trigger 2 and the element 3 performs the phase start of the synchronization unit 4, in which the pulse counter begins to count the clock of the reference generator 13, and the decoder 16 provides the clock synchronization, i.e. generates the signals of the moments of reference for the decisive block 5, carried out by the demodulation of the characters arriving at the character detectors 10-12. The number of undetected characters is counted by a counter of 14 characters. If some number of characters equal to

3

or the logical threshold unit 15 that exceeds the threshold, the start / stop trigger 2 is put into a standby mode ahead of time, before the expiration of the estimated time to code I, this reduces the false busy time during a false phase start (from interference). When properly received, the end point of the calculated duration of the codogram is generated by the decoder of the synchronization unit 4. The signal from the output of the descrambler of the synchronization unit 4 through the element OR 18 is fed to an additional stop input of the start-stop trigger 2 and puts the start-stop demodulator into the standby mode. The decoder 16, connected to the pulse counter of the synchronization unit 4, produces strobe pulses of time intervals for receiving service characters of the codogram, whose position in the codogram is fixed, and

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feeds them to the first input of an additional element AND 17, to the second input of which a signal is received that does not detect the sign from the output of multi-input 5 block 6 coincidence.

If the service character of the codogram is not detected, then the signal from the output of the additional element I I7 through the element OR 18 start-stop 10 demodulator is put into the standby mode regardless of the fact of reception or non-reception of other signs of the cogram.

Since service marks are transmitted in the first bits of the codogram, the start-stop demodulator provides the least free channel in the channel with free access when receiving codograms with service marks, which ensures an increase in the speed of the start-stop demodulator compared to the prototype.

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Claims (2)

1. START-STOP DEMODULATOR according to Autosw.No 4.97741, which requires that, in order to improve performance when working in a channel with free access, a decryptor and an additional element And, as well as an element, are introduced in series into the demodulator OR, while the OR element is connected between the first additional output of the synchronization unit and the additional stop input of the start-stop trigger, the decoder input and the output of the additional element AND are connected respectively to the second additional output of the synchronization unit and W rum input OR gate and a second input of the additional AND gate connected to the output multi-input coincidence unit. 2. The demodulator according to claim 1, wherein the synchronization unit comprises a pulse counter and a first decoder connected in series, as well as a second decoder, the input of which is connected to the output of the pulse counter, the counting and zeroing inputs of the pulse counter being the first and the second inputs of the synchronization unit, and the outputs of the first and second decoders and the output of the pulse counter are respectively the output, the first additional output and the second additional output of the synchronization unit.