SU1356159A1 - Apparatus for controlling synchronized inverter - Google Patents

Abstract

The invention relates to control devices for voltage converters and can be used in power supply devices for electronic equipment. The purpose of the invention is to increase reliability by eliminating inrush current when synchronization is turned on. When the pulses at the output of the synchronizer 1 appear, the master oscillator 3 is turned off and the pulses 5 are not allowed to enter the trigger 5 until the synchronization signal phase coincides with the signal phase at the output of the NAND element 4. To determine the phase matching element AND-NOT 10. 2 Il. i (L with SP O5 SL SO

Description

Phie. R

The invention relates to electrical engineering and may find application in power supply devices for electronic equipment.

The purpose of the invention is to increase reliability by eliminating inrush current when synchronization is turned on.

FIG. 1 shows a block diagram of the device; figure 2 - timing charts of his work.

A device for controlling a synchronized inverter with a transformer output contains a source of 1 clock pulses, the output of which is connected to the input of a time selector 2 pulses, a master oscillator 3 connected to the element

ten; 17 - on the inverse output of RS-trigger 9; 18 - at the output of the generator 3; 19 - at the output of the element AND-NOT 7;

g 20 - at the output of the element AND-NOT 4.

In this mode, at the output of the temporal selector 2 pulses there is a level O (diagram 15 in figure 2). The time selector 2 of pulses 10 provides at the output a signal about the absence of synchronization pulses and a signal 1 in the presence of synchronization pulses. Delay time of the time selector 2 pulses

15 is chosen equal to the pause duration of the synchronization signal. From the output of the time selector 2 pulses, the signal O is fed to the P input of the RS flip-flop 9, providing at its inverse

AND-NO 4, trigger 5, connected to in-20 output level 1 (chart 17 on

the driver 6, the additional element AND-NOT 7, the driver 8 short pulses. The output of the time selector 2 is connected to the R-input of the RS-flip-flop 9, the Z-input of which is connected to the output of the second additional element AND-NOT 10, the first input of which is connected to the output of the forg-shrovator 8 short pulses, and the second

figure 2), which, entering the building input of the master oscillator

3, ensures its operation (Diagram 18 in FIG. 2). With the release of the master

25 generator 3, the signal is fed to the first input of the main element AND-NOT

4. As at its second input there is level 1 (diagram 19 in figure 2), then the output will be input - with the output of the generator 11, there are 30 pulses (diagram 20 in figure 2), short pulses. The inverse output of the RS flip-flop 9 is connected to the gate input of the master oscillator 3. The direct output of the RS flip-flop 9 is connected to the first input of the first auxiliary element AND-NOT 7, the output of which is to the second input of the main element AND-NOT 4, the output of which 11 short pulses are connected to the input of the imager and with the counting input of the trigger 5. The direct and inverse outputs of the trigger 5 are connected to the control inputs of the synchronized inverter 6 with the transformer output.

The device works as follows.

Consider the operation of the device in stand-alone mode in the absence of pulses at the output of source 1, the synchronous ones arrive at the counting input of trigger 5. From the direct and inverse outputs of trigger 5, pulses with a follow-up period T. / 2 control the operation of the synchronized inverter 6 with transformer output .

T

When pulses appear at the output of the source 1 of 40 pulses synchronizing them (diagram 12 in figure 2), the level 1 is set at the output of the temporary selector 2 of pulses (diagram 15 in figure 2). However, switching off the master oscillator 3 and the resolution for the passage of synchronization pulses to the input of trigger 5 will not occur until the phase of the synchronization signal coincides with the phase of the signal at the output of the main elementary pulses (diagram 12 50 AND-NOT 4. To determine the coincidence Fig. 2). The pulse phase of the pulse serves as the second doHon of Fig. 2: signal diagrams are shown: 12 - at the output of the source 1 of synchronizing pulses; 13 - at the output of the first shaper 8 short pulses; 14 - at the output of the second shaper I1 short pulses; 15 - at the output of the selector 2; 16 - at the output of the element AND NOT

ten; 17 - on the inverse output of the RS flip-flop 9; 18 - at the output of the generator 3; 19 - at the output of the element AND-NOT 7;

20 - at the output of the element AND-NOT 4.

In this mode, at the output of the temporal selector 2 pulses there is a level O (diagram 15 in figure 2). The time selector 2 pulses provides the output of the gfy signal for the absence of synchronization pulses and a signal 1 in the presence of synchronization pulses at the output. Delay time of the time selector 2 pulses

is chosen equal to the duration of the pause of the synchronization signal. From the output of the time selector 2 pulses, the signal O is fed to the P input of the RS flip-flop 9, providing at its inverse

figure 2), which, entering the building input of the master oscillator

3, ensures its operation (figure 18 in figure 2). With the release of the master

generator 3, the signal is fed to the first input of the main element AND-NOT

4. Since at its second input there is a level 1 (diagram 19 in Fig. 2), then the output will be sent to the counting input of the trigger 5. From the direct and inverse outputs of the trigger 5, the pulses with the tracking period T. / 2 control operation of synchronized inverter 6 with transformer output.

When pulses appear at the output of the synchronizing pulse source 1 (diagram 12 in figure 2), the output of the time selector 2 of pulses sets level 1 (diagram 15 in figure 2). However, the switching off of the master oscillator 3 and the resolution to the passage of synchronization pulses to the input of the trigger 5 will not occur until the phase of the synchronization signal coincides with the phase of the signal at the output of the main element

An additional AND-NOT 10 element. To more accurately determine the coincidence of the phase of the pulses to the inputs of the second additional element of the NE-10 10, the synchronization pulses are fed through the first driver of the 8 kopoTKoro pulse (Figure 13 in Fig. 2), and the pulses from the output of the main element

That NAND 4 is fed through a second short pulse shaper 11 (Figure 1D in Figure 2). When the pulses coincide at the inputs of the second additional element AND-NOT 10, a transition occurs to the synchronous mode of operation. A signal with a level O (diagram 16 in figure 2) appears on the S input of the RS flip-flop 9, which provides the appearance of a level O on its inverse output (diagram 17 in figure 2). The master oscillator 3 is turned off and on output is set to level 1 (Figure 18 in FIG. 2). From the direct output of RS-flip-flop 9, signal 1 is fed to the first input of the first additional element IS-HE 7 and allows the synchronization signal to pass through the first auxiliary and main elements IS-HE 7 and 4 to the counting input of trigger 5.

The accuracy of determining the moment of phase coincidence is determined by the pulse duration at the output of the short pulse formers. The shorter the pulses, the more accurate the determination of the moment of phase coincidence. The maximum duration of the process from the filing of synchronization to the transition to work in synchronization mode can be determined by the formula

t

ET l Fcn2

 g

- t

X T

at

T, T - the duration of the period

at

 ZG

 R

   - 2

source of synchronizing pulses and 40 master oscillator, respectively; - pulse duration at the output of the first and second 45. shaper short pulses.

highs 50 are commonly used in sync pulse sources

mobile quartz oscillators, and RS oscillators in master oscillators. Therefore, the time to enter synchronization mode usually does not exceed several tens of synchronization periods.

o 5 0

50

five

0 5.

0

594

Thus, the reliability of the device is enhanced by eliminating

Inrush current when synchronization is turned on, which is explained by the absence of an asymmetric mode of magnetization of the inverter transformer when the source of synchronizing pulses is turned on.

Claims (1)

Invention Formula A device for controlling a synchronized inverter with a transformer output, containing a source of synchronizing pulses, a temporary selector of pulses, a master oscillator with a gate input, an AND-NES element, a counting trigger, the output of the source of synchronizing pulses connected to a time selector of pulses, the OUT of the master oscillator is connected to the first input of the NAND element, the output of the NAND element is connected to the counting input of the trigger, whose outputs are intended to be connected to the control inputs of the inverter, from It is curious that, in order to increase reliability by eliminating the inrush current when synchronization is turned on, it is equipped with two short pulse shapers, two additional AND-NOT elements and an RS trigger, and the output of the sync pulse source is connected to the first input of the first additional pulse. element AND-NOT directly and through the first driver of short pulses with the first input of the second additional element AND-NOT, the output of which is connected to the S-input of the RS flip-flop, the R-input of which is connected to By the time pulse selector stroke, the inverting output of the RS flip-flop is connected to the gate input of the master oscillator, the non-inverting output of the RS flip-flop is connected to the second input of the first additional NAND element, the output of which is connected to the second input of the main NAND element, which output is through the shaper pulses connected to the second input of the second additional element AND-NOT " Compiled by A.Pridatkov Editor T.Laeorenko Tehred L.Serdyukova Proofreader L.Pilipenko Order 5807/51 Tlrazh 659Subscribe VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4