SU1348830A1 - Device for computing angle sine and cosine by table method - Google Patents

Abstract

The invention relates to computing and can be used autonomously in high-speed computers or as functional expanders in large computers. The aim of the invention is to improve the accuracy of calculations by eliminating the method error by using an additional address code and eliminating the function overshoot at zero argument values. The device contains a sine register 1, a cosine register 2, a memory block 3, an adder 4, a switch 5, a group of elements NOT 6, an input 7 specifying a function type, an argument register 8, a depot 9 characters, a mode decoder 10, an argument 11 input, the OR element 12. element And 13. 1 ill. T // (L UJ W

Description

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The invention relates to computing and can be used antonomically in high-speed computers or as functional expanders in large computers.

The aim of the invention is to improve the accuracy of calculations by eliminating the method error by using an additional address code and eliminating the function overshoot at zero argument values.

The drawing shows the functional diagram of the device.

The device contains a sine register 1, a cosine register 2, a memory block 3, an adder A, a switch 5, a group of elements NOT 6, an input 7 specifying a function type, an argument register 8, a decoder 9 characters, a decoder 10 mode, an argument 11 11, the element OR 12, element and 13.

The device works as follows.

The memory block 3 contains a table of sine code values corresponding to the function of the first quadrant. The interval of representation of the period T of the function corresponds to the maximum value. n-bit code of the argument (m 2). The argument enters the converter, from the n bits of register 8 of the argument, in which the argument is written to input 11. With the output at 7, a signal about sampling one function from the pair (sin x or cos x) for the argument, which is in register 8 of the argument The mode decoder 10 permits the passage of the iepe-switch 5 argument either directly, plbo p (: .br; yy code.

For argument values in bits n and n-1 00 (T quadrant), the address of the function sin X is formed through the forward code (PC), and the address of the function cos x through the reverse code (OK). For the argument value in bits n and n-1, respectively, 01 (L quadrant) of the address of the function sin X is formed through OK, the address of the function cos x is formed through the PC. For argument values in bits n and n-1, respectively, 10 (III quadrant) is the address of the function sin x is jyeTCH via the PC, and the address of the cos X function is via the CS. For the values of the argument B bit n and n-1, respectively, 11 (IV quadrant) health function

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sin X is formed through the OK, and the address of the cos X function via the PC.

In the accumulator A, the address P of the constant memory block 3 is formed.

If the transfer of the argument by the decoder 10 mode is resolved to the PC, the value of the argument arrives at the input of the second term of the adder 4

10 unchanged. If the transfer of the argument by the decoder 10 mode is resolved to OK, the OK of the lower order bits of the argument is received at the input of the second term of the adder 4.

15 When in the p-2 lower-order bits the argument in the PC contains only zeros, only a few are received from the group of elements NOT 7 at the input of the second term, the signal at the input of the first term 20 is zero. The address in this case is formed from all units and corresponds to the point of the table. Otherwise, a unit is added to the value of OC to the least significant bit.

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Claims (1)

Invention Formula A device for calculating the sine and cosine of an angle by a tabular method containing the argument register, the sine register, the cosine register, the memory block, the adder, the switch, the group of elements NOT, the character decoder and the decoder mode, the outputs of the (n-2) -high-order bits of argument 35, (the p-argument width) is connected to the first information input of the switch, the second information input of which is connected to the outputs of the NOT elements of the group whose inputs are connected to the outputs of the (n-2) -highr bits of the argument register, the outputs of the nth and (nl) -ro bits of which are connected respectively to the first and second inputs of the character decoder, the output of which and the output of the n-th bit of the argument register are connected to the inputs of the higher sign bits of the cosine and sine registers, respectively, the information inputs of the lower bits  which are connected to the output of the memory unit, the address inputs of which are connected to the output of the adder, the control input of the switch is connected to the first output of the mode decoder, the first. 5 Bbifi and the second inputs of which are connected by i.bi respectively with the output of the (n-1) - th bit of the register of the argument and the input specified 1 type of device functions 45  1348830 different from that connected to the first input of the element that, in order to improve the accuracy of you-I, the second input of which is connected to numbering, the device is an additional output of the mode decoder, contains the element AND and the element OR, the output of the element AND is connected to what the outputs of the (n-2) -s minor bits of the first component of the adder, the argument register is connected to the input of the second term of which element OR, the output of which is connected to the output of the switch.