SU1347188A1 - Delta-modulation digital filter - Google Patents

Abstract

The invention relates to computing. Its use in digital processing systems for random processes simplifies the filter if the number of coefficients of the impulse response is 2, where k is an integer. The digital filter contains a linear delta modulator 1, a block of 2 permanent memory (storing coefficients), an equivalence element 3, a reversible counter 4, a block of 5 switches, a block of 6 operational memory, adders 7 and 8, a digital-analog converter 9 and a control unit 10. The execution of block 10 on the clock generator 11, the counter 12 and 13, the element 14 OR-NOT ,, the adder 15 and the imaging unit 16 pulses provides a simplified filter circuit. 2 Il. with (L with 1 00 CX)

Description

The invention relates to computing and can be used in digital processing systems for random processes.

The purpose of the invention is to simplify the filter with the number of coefficients of the impulse response 2 (k is an integer).

Figure 1 shows a functional diagram of a digital filter with del - ta modulation; figure 2 - timing charts of his work.

The delta modulated digital filter contains a linear delta modulator 1, a constant memory unit 2, an equivalence element 3, a reversible counting unit 4, a switch unit 5, a random access memory unit 6

the first 7 and second 8 adders, digital-to-analog converter (DAC) 9 and the control unit 10, including a clock generator 11, the first 12 and second 13 counters, a W-NOT 14 element, an adder 15 and a pulse shaper 16. In addition, the digital filter contains the input 17, the source 18 of the logical zero and the code 19 (figure 1).

 The delta modulation digital filter operates as follows.

Clock pulses (figure 2) from the output of the clock generator 11 with the frequency M / T, where M is the number of weights; Td is the sampling period, it arrives at the input of the first counter 12, at the output of which overflow a pulse is formed with a frequency Td (Fig. 2b). On the leading edge of the latter, the output signal C} LDM 1 is compared. In the sampling interval 10, the signal from LDM 1 (FIG. 2) is sent to one of the inputs of the equivalence element 3, to the second input of which the coefficient

The recipients L,}, k o, M-1J, each over time Td (Fig. 2 g). The order of change of the coefficients is constant and is specified by the first counter 12. The result of the multiplication

W (h

The input signal Li-Lc is applied to the coefficients at the input of the reversible counter 4. At time intervals t ,, t,, reading is performed from the operative memory block 6 and, according to the installation inputs to the reversing counter 4, the signal corresponding to the incomplete

convolution On the trailing edge of the clock pulse (Fig. 2a), the signal recorded in counter 4 is summed with the result of multiplying the input signal by the coefficient of the impulse response. At intervals, 1, etc. The accumulated signal value (corresponding to incomplete convolution) is recorded in the same cell of the RAM block 6 via the switch block 5. The switches of block 5 are in the first position (DO UQ) - in this case there is no pulse (Fig.2 d) from the output of the element OR NOT 14. The cell numbers of the RAM 6 are determined by the second counter-13 and the adder 15, which recycle them

(figure 2 g)

Such a signal accumulation in the form of incomplete convolution occurs over all time intervals T.

except to, tj, when a pulse appears (Fig. 2 d) from the output of the element OR NOT 14. This pulse converts the switches of block 5 to different positions at which Uj U) 2 0. As a result, over the interval

time t, the recording of O occurs in the corresponding cell of the RAM 6. And at time t (on the trailing edge of the clock pulse) a signal corresponding to the complete convolution (i.e., containing M terms) is generated from the signal recorded in the reversible counter 4. At time t, the leading edge of the pulse from shaper 16 (Fig. 2e) is summed by the specified signal in adder 7 with the accumulated signal, and the trailing edge of the pulse from shaper 16 (at time t) is summation of the output signal of adder 7 with the previous sample of the output signal of the filter in the summator 8. Thus, in the adder 8, the current sample of the output of the frutration signal is formed in the format of pulse code modulation. With the help of the DAC 9 signal at | prev

 to analog form y (t).

Thus, when choosing the number of coefficients M 2., The filter circuit is simplified due to the fact that blocks 12 and 13 can be k-bit counters with parallel

output code, and block 15 - 2k-BxoAOBoft full adder.

Claims (1)

Invention Formula A delta modulated digital filter containing a linear delta modulator whose output is connected to the first input of the equivalence element, the output of which is connected to the counting input of a reversible counter, the outputs of which are connected to the first inputs of the switch block, the outputs of the switch block are connected to the information inputs of the block memory, the outputs of which are connected to the installation inputs of the reversible counter, the block of permanent memory, the output of which is connected to the second input of the equivalence element, the first and Secondary adders, a digital-to-analogue converter and a control unit, the information input of a linear delta modulator is a filter input, characterized in that, in order to simplify the filter with the number of impulse response coefficients 2, (k is an integer, block. control is performed on the counters, the adder, the pulse generator, the element OR NOT and the clock generator, the output of which is connected to the counting input of the first counter, the clock input of the clock 188 l I impulse And to the control 11 inputs of the reversible counter and RAM, the bits of the first counter are connected to the first inputs of the adder, the inputs of the OR-H element and to the address inputs of the permanent memory block, the overflow output of the first counter is connected to the counting input of the second the counter and the clock input of the linear delta modulator, the outputs of the second counter are connected to the second inputs of the adder, the outputs of which are connected to the address inputs of the RAM, the output of the element OR is NOT connected to the information input One pulse generator and to the control input of the switch unit, the second information inputs of which are connected to a logical zero source, the output of the pulse generator is connected to the synchronization inputs of the first and second adders, the first information inputs of the first adder are connected to the outputs of the reversible counter, the outputs of the first adder are connected to its outputs the second information inputs and the first information inputs in the turns of the second adder, the outputs of which are connected to its second information inputs and inputs ifrranalogovogo converter, whose output is the output of the filter. tpuz.Z Compiled by O. Revinsky Editor I. Shulla Tehred A. Kravchuk Proofreader S. Cherni Order 5128/52 Circulation 899 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4