SU1347165A1 - Process sequence generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in computing, automatic control systems and information transmission systems. The purpose of the invention — extending the functionality — is achieved by providing control over the period formed by the pseudo-random sequence. For this, a second counter 2 pulses, a second memory block 7, an adder 8 modulo two and a register 9 are entered into a pseudo-random sequence generator. In addition, the device contains the first counter 1, a clock generator 3, the adder 4, the first memory block 5 and & management The change in the duration of the generated sequence is carried out by changing the information in the memory block 7. The functional diagram and the element-by-element composition of the control unit 6, as well as timing diagrams explaining the operation of the device, are given in the description of the invention. 3 il. (L 0n W 4 1 about: Cfl to / x

Description

The invention relates to a pulse technique and can be used in computing, automatic control systems and information transmission systems.

The aim of the invention is to enhance the functionality by providing control over the period of the pseudo-random sequence being generated.

FIG. 1 shows a block diagram of a pseudo-random sequence generator; in fig. 2 - timing charts of the control unit; in fig. 3 is a control block diagram.

The pseudo-random sequence generator (Fig. 1) contains the first 1 and second 2 pulse counters, the generator: 5 clock pulses, adder 4, first memory block 5, control block 6, second memory block 7, adder 8 submodule two, register 9, the information input of which is connected to the output of the first memory block 5 and the input of the adder 8 modulo two, the output of which is connected to the information input of the first memory block 5, the address inputs of which are connected to the corresponding outputs of the adder 4, the inputs of the first group of inputs of which are connected to The corresponding outputs of the second counter 2 pulses, the synchronization input of which is connected to the fifth output of the control unit 6 and the installation input of the adder 8 modulo two, the synchronization input of which is connected to the first output of the control unit 6, the second output of which is connected to the synchronization input of the first memory block 5 . The clock generator 3 output is connected to the synchronization input of control unit 6 and the synchronization input of the first pulse counter 1, the installation input of which is connected to the third input of control unit 6, the inputs of which are connected to the corresponding outputs of the first group of outputs of the second memory block 7 whose input inputs are connected to corresponding outputs of the first counter 1 pulses. The outputs of the second group of outputs are connected to the corresponding inputs of the second group of inputs of the adder 4. The fourth output of the control unit 6 is connected to the synchronization input of the register 9.

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The control unit 6 (Fig. 3) contains a decoder 10, a pulse shortening circuit consisting of successively connected RC circuits, a first 11 and a second 12 HE elements, and a pulse shaping circuit consisting of serially connected third HE elements 13 and element 14. The connection of the outputs of the control unit 6 with other units of the device is shown by the corresponding numbering of the outputs of the control unit 6 (Fig. 3).

The pseudo-random sequence generator works as follows.

At time t (Fig. 2), the first counter of the 1 pulses and the adder 8 modulo two are in the zero state. The content of the i-th cell of the first memory block 5 is fed to the input of the adder 8 modulo two. At time t2, the pulse from the first output (Fig. 26) of the control unit 6 information from the output of the first memory block 5 is recorded in the adder 8 modulo two. At time t, the pulse from the generator output 3 clock pulses (Fig. 2 and) changes the state of the first pulse counter 1. In this case, at the outputs of the second group of outputs of the second memory block 7, the relative address of the j-th cell of the memory block 5 is set, the information from the output of which at the time t according to the pulse from the first output (Fig. 2) of the control block 6 is folded modulo two information previously recorded in sum - mat 8 modulo two. At a time instant tj, the state of the first pulse counter 1 is changed, and at the output of the second memory block 7 a relative address of the Kth cell is set, the contents of which are summed with the contents of cum1 1mator 8 modulo two at time t. At the same time, the pulse from the fourth output (Fig. 29) of control unit 6 simultaneously records information from the output of memory block 5 to the register 9, i.e. change information at the output of the device. At time t, after changing the state of the pulse counter 1 at the output of the second memory block 7, a relative cell address of the memory block 5 is set, into which the pseudo-value formed in modulator 2 is written

Claims (1)

tea sequence. The recording is made at the moment t in momentum (Fig. 2 g) from the second output of the control unit 6. At the moment of time tg, the change of state of the counter 1 of pulses initiates the appearance at the third output (Fig. 2e) of the block 6 of the control of the zero pulse of the counter of 1 pulses. After setting the counter 1 pulses to the zero state at time t on the fifth output (Fig. 2b of the control unit 6, a zero-impulse pulse of modulator 8 modulo two and a change of the base address is generated (to add it to the relative address: output unit 7 memory in the adder 4) at the output of the pulse counter 2. Next, the cycle of generating the new value of the pseudo-random sequence is repeated. Changing the length of the generated sequence is carried out by changing the information in block 7. A pseudo-random sequence generator, containing a clock pulse generator, the output of which is connected to the synchronization input of the first pulse counter, a modulo two adder, the output of which is connected to the information input of the first memory block, which is different in order to expand its functionality by providing adjusting the period of the generated pseudo-random sequence, a second pulse counter, a second memory block, a register, a control block and an adder are entered into it, the inputs of the second pulse counter are connected to the first group of inputs of the adder, the first group of outputs of the second memory block is connected to the corresponding inputs the control unit, the information input of the register is connected to the output of the first memory unit and the input of the modulo-two adder, the input; synchronization of which is connected to the first output of the control unit, the second output of which is connected to the synchronization input of the first memory unit, the address inputs of which are connected to the corresponding outputs of the adder, the second group of inputs of which are connected to the second group of outputs of the second memory block, address the inputs of which are connected to the outputs of the first pulse counter, the installation input of which is connected to the third output of the control unit, the synchronization input of which is connected to the output of the clock generator, - input b chronization register coupled to the fourth output of the control unit a fifth output is connected to the input for setting modulo two adder and to the input of the second sync pulse counter. : |: / f Zbe.J Editor I. Shulla Compiled by Y. Burmistrov Tehred I.PopovichKorrektor A. Tsko Order 5127/51 Circulation 899 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4