SU1256027A2 - Device for generating memory addresses - Google Patents

Abstract

The invention relates to computing, can be used in automated systems for identifying information, working in real time. The purpose of the invention is to increase speed. The device contains an input register 1, a group of switches 2 -2, a group of decoders 3, -3, an address code, an adder 4, three flip-flops 5, 17, 18, two elements 6, 13, a counter 7, a decoder 8, a multiplexer 9, a group registers, delay delay group, element OR 12, register 14, comparison circuit group, encoder 16, delay element 23. This set of features makes it possible to achieve the purpose of the invention. 1 silt, 1 tab. (L tc sp about o tc N3

Description

The invention relates to computing technology and can be used in automated information identification systems operating in real time and is an improvement of the device according to the author. St. No. 928358.

The purpose of the invention is to increase the speed,

The drawing shows a block diagram of the proposed device.

The proposed device contains an input register 1, switches,

ten

18 - in a single state. A code of the information number (an object consisting of K ods of characters (ranks) is fed to the device input 21. The signal for starting the formation of the address is fed to the input 19 of the device and sets the trigger 5 to one, thereby allowing the sync pulses from the device input 20 to pass through the element And 6 to the counting input of the counter 7. The first sync pulse that passed through the element And 6, will change the contents of the counter 7 and cause a signal on the first output of the decoder 8 signal, according to which

decoders 3-t., address code, adder 4, trigger 5, element 6, count-15 trigger 18 will go to zero state 7, decoder 8, multiplexer 9, registers, delay elements, element OR 12, element AND 13 , register 14, comparison circuits, encoder 16, triggers 17 and 18, 20 inputs 19-21, output 22, delay element 23,

The proposed device works as follows.

After switching on, trigger 5, counter 25

tion, and in register 1 will write the code number of the object. For the time before the next sync pulse, the comparison scheme 15, -15 compares the character codes included in the object number of registers 1 and 14. The result of the comparison encoder 16 converts into a code on the first output and i a signal on the second output in accordance with the table, where O - i-ro codes

characters do not match, 1 - codes j-ro mark

Since the object number code recorded in register 1 is not zero, and register 14 is zero, a zero signal is set at the outputs of circuits 15.-15c. The encoder 16 converts the result of the comparison into a signal at the second output, which resets the trigger 18 through the OR element 12 to the initial state, allowing the passage of the next clock pulse through the AND 6 element.

18 - in a single state. A code of the number of information (an object consisting of K ods of characters (ranks) is fed to the input 21 of the device. The signal of the beginning of the formation of the address is fed to the input 19 of the device and sets the trigger 5 to one state, thereby allowing the sync pulses from the input 20 of the device to pass through the element And 6 to the counting input of the counter 7. The first sync pulse that passed through the element And 6, will change the contents of the counter 7 and cause a signal on the first output of the decoder 8 signal, according to which

trigger 18 will go to zero

trigger 18 will go to zero

tion, and in register 1 will write the code number of the object. For the time before the next sync pulse, the comparison scheme 15, -15 compares the character codes included in the object number of registers 1 and 14. The result of the comparison encoder 16 converts into a code on the first output and i a signal on the second output in accordance with the table, where O - i-ro codes

characters do not match, 1 - codes j-ro mark

The second sync pulse will cause a control signal to appear at the second output of the decoder 8. Signs and descramblers Z.-W., codes of characters (branch numbers) are supplied. In this case, from the outputs of the switches 2 -2 to the decoders 3 -3, signals are provided to ensure their operation, and from the output of the decoder 3 to the adder 4, the starting address A 1 corresponding to the code of the first character (branch number

3

first level). The third clock pulse from the input of the decoder 3 to the adder 4 is fed the number lA2. In the adder 4, a starting address is formed corresponding to the branch number of the second level A2 A1 + lA2. From the output of the adder, the number A2 is fed to the information inputs of the registers tO, -10 and when a signal arrives, from the third output of the decoder 8, delayed delay element 11, is written to register 10. The next clock pulse from the output of the decoder 3j to the adder 4 is supplied with the number dAZ. In adder 4, a start address is formed corresponding to. branch number of the second level A3 A2 + l AZ. From the output of the adder, the number A3 is written by the signal from (k +, 1) to the output of the decoder 8 to the register U

Upon completion of the conversion of the object number code, the corresponding start address is set at the output 22 of the device, and the counter overflow output generates a signal on which the trigger 5 is set to the initial, zero state and the register 1 is copied to the register 14.

. The device is ready to form an address using the following object number code.

The initial state of the registers for the second and subsequent address generation cycles is as follows.

Registers 1 and 14 contain the code of the object number of the previous cycle, and registers contain the corresponding starting addresses calculated in the previous cycle.

The operation of the device for the second and subsequent address generation cycles will be considered on the example of the formation of the address of an object of rank 4 (i.e. the object number consists of four digits

for example, a, a, a, b) by code

but.

the object number, which up to the third digit inclusively coincides with the code number of the object of the previous cycle - recorded in register 14. At the first clock pulse, the first output of the decoder 8 is a signal, by which the trigger 18 is set to zero state, and Register 1 records the code of the object number. Signal 1 is set at the outputs of all comparison circuits, and output 15 of the circuit 15 is compared, the signal O.

g S 5.

20

25

here

2560274

forms the result of the comparison (see table 1 in room 4, the signal at the second output is missing.

A trigger 18 by a zero signal at the direct output prevents the next sync pulse from passing through element 6 and allows the signal from the inverse output to pass the second clock through element 13 to the record input of counter 7. The code 7 from the information input records the code from the first output of the encoder 16. Trigger 17 is set to the zero state. On the decoders 3 -3, the control signal is not received, since the decoder 8 is turned off by a zero signal from the output of the trigger 17 applied to its information input. From the output of counter 7, the code of the encoder 16 is given to the control input of the multiplexer 9. The multiplexer 9 outputs the contents of register 10, which is fed to the adder 4. Thus, the starting address A3 corresponding to the branch number of the third level is written to the adder 4 computed as far back as the previous cycle. The next sign in the object number is different from the sign in the object number of the previous cycle, therefore the trigger 18 is reset to the initial state by signal from delay element 23, allowing the subsequent sync pulses to pass through the AND 6 element to the counting input of counter 7. The third clock pulse passes 17 returns to the initial state and turns on the decoder 8, from the fifth output of which the control signal goes to the decoder 3. From the output of the decoder 3. A number DV4 is fed to the adder 4. In the adder 4, the starting address of the object of the fourth rank B4 A3 + iB4 is formed already after the third clock pulse.

five

0

Claims (1)

Invention Formula Device for generating memory addresses by aut. St. No. 928358, which is related to the fact that, in order to increase speed, K comparison schemes (k is the number of ranks of address information), an encoder, a group of K registers, a group of i delay elements, a register, a multiplexer, the second and the third trigger, the delay element, the second And element and the OR element, and the installation input in O of the first trigger is connected to the counter overflow output, the information input of which is connected to the first output of the encoder, the second output of which is connected to the first input of the OR element, the second input of which is inen with the output of the delay element, the input of which is connected to the output of the second element I, the recording input of the counter AND the installation input to O of the second trigger, the installation input in 1 of which is connected to the output of the first element I, the information output of the counter is connected to the control input of the multiplexer, strobe input which is connected to the direct output of the third trigger and the first input of the second element AND, the second and third inputs of which are connected respectively to the output of the first trigger and the device synchronization input, the output cell of the OR element connected to the input of the installation of the third trigger, the inverse output of which is connected to the third input of the first element I, the input Editor S.Patrusheva Compiled by Y.Lantsov. Tehred L.Serdyukova Proofreader V.Sinitska Order 4824/48 Circulation 671. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 The settings of the 1st third trigger are connected to the first output of the decoder, the output of the second trigger is connected to the gate input of the decoder, the third –fth to (k + 1) -th outputs of which are connected to the inputs Respectively from first to. the delay elements of the group whose outputs are connected to the inputs of the record of the same register of the group, the information inputs of which are connected to the output of the adder, (k + 1) -th input of which is connected to the output of the multiplexer, the first to and informational inputs of which are connected to the outputs of the same name registers of the group, from the first to the k and the outputs of the input register are connected to the first inputs of the same name comparison circuits of the group and to the information inputs of the register of the same name, from the first to K, and the outputs of which are connected to the second inputs of the same name comparison circuits of the group, the outputs of which are connected to the same inputs of the encoder.