SU1345366A1 - Signal shaper - Google Patents

Abstract

The invention relates to radio engineering and improves noise immunity by eliminating clock frequency failures. The device contains the reference Mr. 1, dividers 2, 3, 4 and 8 frequencies, el-5, - el-OR 6, manipulator 7 frequencies. Newly introduced elements And 9 and elements OR 10. 1 Il. 1 (/ с 4 СП СО О5 о

Description

This invention relates to radio engineering and may find prignenie in digital devices for transmitting information.

The purpose of the invention is to increase the number of tolerances, resistance by eliminating clock frequency failures.

The drawing shows a structural-electrical circuit of the device.

The device contains a reference oscillator 1, the first frequency divider 2, the second frequency divider 3, the third frequency divider 4, the first element AND 5, the first element OR 6, the frequency manipulator 7, the fourth divider 8 frequencies - you, the second element AND 9 and the second element OR 10.

The device works as follows.

Let all three frequency dividers 2-4 work without failures in the account. Then, at the outputs of the first, second, and third frequency dividers 2-4, is: o-short pulses with frequencies of 2f, 2f, and F, respectively. Out of the first and second frequency dividers 2 and 3, the first element And 5 selects short pulses of coincidence with the clock frequency. Since the output pulses of the first element 5 are fed to the installation input of the third frequency divider 4, it is synchronized with the operation of the first and second dividers 2 and 3 frequencies,

Consequently, the output pulses of the third divider 4 frequencies have a frequency and phase (time of occurrence) exactly equal to the frequency and phase of the output pulses of the first element AND 5. The synchronization mode is also supported by the fact that the output

the pulse signals of the first and second frequency dividers 2 and 3 are transmitted through the second element OR 10 to the first input of the second element 9, to the second input of which the output signal from the third frequency 4 separator is fed. Since, when all three dividers of 2–4 frequencies work correctly, their output signals occur synchronously, the second element AND 9 separates pulses whose frequency is equal to the clock F, and these pulses are exactly synchronous with the pulses at the output of the first element AND 5. The output pulses of the second element And 9 arrive at the installed inputs of the first and second

dividers 2 and 3 frequencies, synchronizing their work.

The output pulses of the first and second elements AND 5 and 9 are synchronous and in-phase, therefore, the summation in the first element OR 6 of these pulses leads to the formation of a pulse signal with a clock frequency F. These pulses can be used.

Used to synchronize various communication system devices. In the proposed device, the output signal of the first element OR 6 is fed to the synchronizing input of the frequency manipulator 7, to the two information inputs of which two output signals of the first and second dividers 2 and 3 frequencies and frequencies 2f- and 2f are fed separately, and to its control input digital coded message. If information element 1 acts on the control input of the frequency manipulator 7, then starting from the moment of arrival}, a short clock pulse to its clock input and to the end of the clock interval, the frequency manipulator 7 passes the signal of the first divider 2 frequency with a frequency of 2f to its output . If the information element O acts on arrival of the next clock pulse at the control input of the frequency manipulator 7, then, starting from the moment of arrival of the short clock pulse and to the end of this clock interval, the frequency manipulator 7 passes the signal of the second divider 3 frequency to its output . The output signal of the frequency manipulator 7 is fed to the input of the fourth frequency divider 8, the output oscillation of which has a frequency f, during the clock interval if information element 1 is transmitted, and the frequency f-, during the clock interval if information element is transmitted A. The resulting oscillations are a signal with a minimum shift manipulated, which is a frequency-controlled oscillation without phase discontinuity and a manipulation index of 0.5. Correct formation of such a signal is ensured by proper selection of the division factors of all dividers of 2–4 frequencies, determined by the condition of the correct ratio between the frequencies to be manipulated and the clock frequency, as well as

the work of the first, second and third dividers 2-4 frequencies without failures.

Suppose that c6oyf in the account occurred in the work of only the first divider 2 frequencies, In this case, at the right clock point in time, the output pulses of the first and second dividers 2 and 3 frequency do not coincide, and at the output of the first element I 5 at the clock moment of time arises. However, due to the condition, the second frequency divider 3 is operating normally, and its output pulse appears at the same time. This pulse through the second moment of RSHI 10 is fed to the first input of the second element I 9, to the second input of which at the same time the output pulse of the third divider 4 frequencies is applied, since it is operating normally. As a result, at the output of the second element I 9, exactly at the clock moment of time, a pulse arises, which through the first element OR 6 enters the synchronizing input of the frequency manipulator 7, ensuring the correct formation of the signal. In addition, this pulse from the output of the second element And 9 is fed to the setup inputs of the first and second dividers 2 and 3 frequencies, in sync with the operation of the first divider 2 frequencies, in which there was a failure, and confirming the correct operation of the second divider 3 frequencies.

Since the clocking signal is obtained using the first And 5 element connected to the outputs of the first and second dividers 2 and 3 frequencies, the processes of correcting the clocking error in case of failure S of the second divider count 3 frequencies are similar to those indicated.

If only the third splitter of 4 frequencies fails to count, the clocking pulse is assigned to the first element of AND 5, since the first and second dividers of the 2 and 3 frequencies work normally. This pulse through the first element OR 6 is fed to the synchronizing input of the frequency manipulator 7, ensuring the correct formation of the signal, and, moreover, to the installation input of the third frequency divider 4, synchronizing its operation and thereby eliminating the error in it in the temporary position its output pulse relative to the exact timing of the clock.

Thus, the device eliminates clocking errors with itself in the count of any one of the three dividers of 2-4 frequencies.

The use of the second element AND 9 and the second element OR 10 in the proposed device, as well as the introduction of an additional connection between the output of the first element AND 5 and the installation input of the third frequency divider 4, improves the noise immunity of the driver due to the fact that a failure in the count of one of the three dividers 2 The –4 frequencies included in the device do not even lead to a short-term change in the clock frequency, and since the clock and the manipulated frequencies in the signal manipulated with the minimum shift are closely related, this does not occur. um failure in the formation of the signal itself.

Since in the device a failure in the counting of one of the three dividers of 2-4 frequencies does not lead to any changes in frequency and phase, and consequently, in the temporary position of the clock pulses, its use in modems provides a higher overall noise immunity. This is due to the fact that the clock synchronization signal in the signal demodulators manipulated with a minimum shift is obtained by additional mutual processing of the filtered signals with frequencies equal to the manipulated one and subsequent narrowband filtering. Thus, if a failure occurs in the duration of only one clock interval in the signal conditioner, the temporal position of all other clock points in time, following a fault, is shifted. Since the inertia of the clocking signal filtering devices is high, the signal demodulator for a long time operates with incorrect synchronization, which reduces the noise immunity of signal reception. In the device, this can occur only in the case of simultaneous failure of two counters, and the probability of this event in case of independent counters is equal to the product of the probabilities of failure of the counters. If the counters are the same, the probabilities of their failure can be accepted by the soldiers, and in the case of ensuring good disconnection of the microcircuits of the counters on power, the failures in the operation of the counters can be considered independent. For such operating conditions, the probability of device failure is equal to the square of the probability of a single counter being used.

Claims (1)

Invention The signal shaper contains a reference oscillator, the output of which is connected to the information inputs of the first, second and third frequency dividers, and the outputs of the first and second frequency dividers are connected to the information inputs of the frequency controller and the inputs of the first And element, the output of which The first OR element is connected to the clock input of the frequency handler, the output of which is connected to the input of the fourth frequency divider, the output of which is Editor S. Lisin Order A933 / 56 Compiled by O. Andrushko Tehred L.Serdyukova Proofreader M.Maksimishined Circulation 635 Subscription VNSHSHI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 the signal generator, whose input for the digital coded message of which is the control keypad input, is characterized in that, in order to improve noise immunity by eliminating clock frequency failures, the second OR element and the second element AND are entered, the second input which is connected to the output of the third divider, the output of the second element AND is connected to the second input of the first element OR and the installation inputs of the first and second frequency dividers, the outputs of which are connected to the inputs of the second element OR, and the input of the first element AND is connected to the setup input of the third frequency divider.