SU1339573A1 - Data exchange control device - Google Patents

Abstract

The invention relates to exponential techniques and can be applied to control external devices that are connected to several input / output channels of a computer. The aim of the invention is to increase speed. The device comprises an information transmission unit 1, a delay control unit 7, a group of elements OR 3, three elements OR 4, 5, 6, and element 2. ZP f-ly, 4 ill. 1L “12; oo co-ate with J3 8 channel I Figure 1

Description

The invention relates to a single technology and can be applied to control external devices that are connected to several computer input / output channels,

The purpose of the invention is to increase speed by introducing a mode that reduces the access time to a occupied device after it is released.

Fig, 1 shows a block diagram of the device; 2 is a functional diagram of a delay control node; figure 3 - the algorithm; Fig 4 is a temporary diagram of the operation of the device ..

The device (FIG. 1) contains an information transmission unit 1, an element AND 2, a group of elements OR 3, a first 4, a second 5 and a third 6 P1LI elements, a UAE 7 delay control, inputs 8-13, outputs 14-19,

The control node of the delay (fig. 2) contains a counter 20 and mycov, a counter of 21 cycles, a comparison element 22, a trigger 23, six elements AND 24-29, two elements OR 30 and 31, and two elements HE 32 and 33,

The device works as follows

Three modes of operation of the device for controlling data exchange are possible.

The mode with the immediate answer about the busy device,

In this mode, at the device input 13, the signal Setup mode is absent and pulse counters 20 and cycles 21 are previously reset with the Reset signal at device 12. At the exit of the element 22 cfr-. Therefore, at the third output of the delay control unit 7, there will be a Comparison signal, which is permissive for element 2 and does not prevent the formation of a Short Sample signal in the device.

In this mode, the device operates like a known device,

Setup mode (previous to third mode).

This mode is set once when the system is turned on, the device is a channel. A belt of this mode is shown in FIG. 4.

In the initial state, trigger 23, pulse pulsers 20 and cycles 21 are reset. On rrr) poN input element

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Both 27 and inopoM in the same way; r; i 29 nptscyTf.TBye-r p, 4rjv oniaianHii signal from the output of the element 111, 53, When the signal is pierced The setting mode at the device input 13, the counter 21 cycles changes state to -i-l. Signal Setup mode is then present continuously. At the output of element 29 and, accordingly, at the output 19 of the device, a TRB-A signal appears (subscriber requirement). In response, the channel sets the VBR-K (Channel sampling) signal to the device input 10, which resets the TRB-A signal. The VBR-K signal also permits the arrival of a counting pulse on the device input 1I to the output element I 25, since the fourth input there is an enable signal from the output of the element HE 32, the signal from the output of the element C 25 sets trigger 23, if it was reset, if not, then through elements 26 and OR 30 it arrives at the counting input of the counter 20 pulses and changes its state to + one. As soon as the values of pulse counters 20 and cycles 21 are compared, the output signal of the comparison element 22 appears allowing the signal to be set at the output of the element 28 and then the device 18 output of the FBG-A signal (subscriber sampling), the channel responds by resetting the FBG signal. To the input 10 of the device. This results in resetting trigger 23, pulse counter 20, VBR-A signal, setting the TRB-A signal and changing the state of the counter of 21 cycles by another +1. Then a new cycle begins, and so on.

With each cycle, the delay in the moment when the VBR-A signal is issued increases by the duration of the period of the counting pulse. This process continues until, according to the I / O interface standard. Late issuance of any signal can cause the associated signature to remain in a constant state for an indefinitely long time until the error is eliminated. . In this case, the late issuance of the FBG-A signal leads to the fact that the FBG-K signal is not reset, since an error occurs in the computer I / O channel in this case. After that, the loop counter 21 goes into the setting state, the signal is taken

31

The installation mode from input 13 of the device resets the error in the I / O channel and, accordingly, the FBG-K signal. The latter causes a reset of the counter 20 pulses.

In this mode, the first counting pulse in each cycle does not change the state of the pulse counter 20, but is recorded in trigger 23. Therefore, the number of pulses stored in the counter of 21 cycles reflects the maximum delay time of the VBR-A signal, which does not cause a fault in the input channel. - withdrawal.

The device is prepared for operation in the third mode.

Time delayed mode.

Counter value 21 cycles in

This mode is set to the previous mode. When a device is addressed from the side of the first channel and after the VBR-K signal is installed, a Short Sample signal appears at the corresponding output of node 1. This signal allows the arrival of the counting pulses through the element And, 24 to the input of the counter 20 pulses. Signal flow Short sampling of the output element I 2 to form the UPR-A signal (subscriber control) byte-state of the VHU is blocked by the signal Uncomparison from the output of the comparison element 22.

If the device is free and the signal disappears. A short sample is taken before comparing the values of pulse counters 20 and cycles,. 21, then the first channel will continue the sampling of this device that has begun. In this case, node 1 is not informed by the corresponding input of the signal sample. Short sample, since the second input of the And 2 element contained a inhibit signal.

If the values of pulse counters 20 and cycles 21 are compared, then a short sampling signal appears at the output of the And 2 element, according to which the UTP-A signal is output to the channel with a byte state of the MCU, since in this mode the first the pulse changes the state of the pulse counter 20, then the comparison of the counter values occurs for a period of one counting pulse earlier than it was in the last cycle of the second mode. This allows you to issue

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The UPR-A signal with the byte state of the VLU is occupied with the maximum possible delay for the channel, without causing it to fail.

Claims (1)

Claim 1. Device for controlling data exchange, containing information transfer node, group of elements OR, first element OR, with first and second information inputs of information transfer node being inputs of a device for connecting respectively to information outputs of a first and second computer I / O channels The first and second information outputs of the information transfer node are the outputs of the device for connecting respectively to the information inputs of the first and second channels of computer I / O, the outputs of the elements OR groups form a group of outputs of the device for connecting the information inputs of the first channel of the computer I / O to the group, the output of the first element OR is the output of the device for connecting the subscriber's control of the first channel of the computer to the input, the first inputs the elements of the OR group are connected to the group of information outputs of the information transmission node, the output of which the subscriber’s control is connected to the first input of the first element OR, characterized in that, in order to improve speed, A delay control node, two OR elements, an AND element are entered, the input of the data transmission node sampling is connected to the input of the delay control node and is the device input for connecting to the output. Selection of the channel of the first I / O channel of the computer, sync input, setup input and The operation mode of the delay control node is respectively the synchronous input, the setup input and the installation input of the operating mode of the device, the outputs of the second and third elements. OR are the outputs of the device for connection respectively to the subscriber sample inputs and the subscriber's requirement of the first channel of the computer I / O, the first and second outputs of the delay control node being connected to the first inputs of the second and third OR elements, respectively, the second inputs of which are connected correspondingly to the outputs of the subscriber sample and the subscriber's subscriber demand information, output A short sample of which is connected to the first input of the element AND and to the authorizing input of the delay control node, the third output of which is connected to the second input of the element AND whose output is Inen with the second input elements of the OR group, the first element OR, and with the input Short sample of the information transfer node. 2, The device according to claim 1, about tl and - the fact that the delay control unit contains a pulse counter, a cycle counter, a reference element, a trigger, six AND elements, two OR elements, two NOT elements, and the first input of the first element And is authorizing the input of the delay control node, the first input of the second element AND is connected to the first input of the third element AND, the input of the first element is NOT and is the input of the sample of the delay control node, the installation input of the cycle counter is connected to the first input of the first element OR and mouth By inserting the input of the delay control node, the second input of the first element I is connected to the second input of the second element I and is the synchronization of the node controlling the delay, the third input of the second element I is connected to the first inputs of the fourth and fifth five 0 five 0 five And, with the second input of the third element And and is the input of the operation mode of the delay control unit, the outputs of the third and fifth elements And are respectively the first and second outputs of the delay control unit, the output of the comparison element is connected to the input of the second element NOT, With the third input of the third element And is the third output of the delay control node, while At the delay control node, the output of the second element is NOT connected to the fourth input of the second element X by the third input of the first element AND whose output connected to the first input of the second OR element, the output of which is connected to the counting input of a pulse counter, the output of which is connected to the first input of the comparison element, the second input of which is connected to the output of the cycle counter, the counting input of which is connected to the output of the fourth And element, the second input of which one with the output of the first element NOT, with the second input of the fifth element AND with the second input of the first element OR, which is connected to the installation input of the pulse counter and with the zero input of the trigger, the unit in od is connected to the output of the second AND gate and the first input of the sixth AND gate, a second input coupled to an output of the flip-flop, the output of the sixth AND gate connected to a second input of the second OR gate, Fig 2 Not SI on Bypass Sch. pulse W Sign. TRB-A on SM 19 wap-va Sign. V6R-K on the BZ. Just-Va Signal on the number. 9l.sra6nen.22. CuiH. 8BP-A but Bbia.lBust-va LJI..U1JL. Editor E. Papp FIG. Compiled by S. Pestmal Tehred M.Didzh Corrector S. Cherni Order 4224/40 Circulation 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Z-ZZ, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4