SU1334395A1 - Image display device - Google Patents

Abstract

The invention relates to Lleuvida. The purpose of the invention is to increase the quality of the reproduced image W orz. The device contains a block of video sources 1, a video-digital converter 2, information conversion blocks, a control block 8 and a scan control block 10, the device operates in two independent modes: information recording mode and information reading mode, with both processes aligned in time. The goal is achieved by the introduction of additional information conversion units and a control unit 10 of the scan sludge. 1 MHGH tg TRYTVDgu (L CZ

Description

with

00 4

CO SO

ate

The invention relates to a television technique and can be used to reproduce images on a matrix screen.

The purpose of the invention is to improve the quality of the reproduced image. In FIG. 1 is an electrical block diagram of an image reproducing apparatus; in fig. 2 is a control block diagram; in fig. 3 is a diagram of a reversing scan control unit.

The device for reproducing an image (Fig. 1) contains a block. 1 of video signal sources 5, a video-digital converter (TDC) 2, MxN blocks 3 ij (i 1, M, j 1, N) for information generation, the first and second blocks 4 and 5 memory, control input-6 TDC, first synchronization output 7 TDC control unit 8, second synchronization input 8 TDC, scan control unit 10, third synchronization input 11 TDC, first group of outputs 12 of the control unit, decoding unit 13, second, third, fourth, the fifth and sixth outputs 14-18 of the control unit, the eighth output 19 of the control unit, block 20, output register bits, ninth 21 and tenth 22 outputs of the control unit, fourth 23 and fifth 24 inputs of the control unit, first sync output 25 of the sweep control unit, scanning unit 26, fourth, fifth and sixth outputs 27, 28, 29 of the control unit sweep, display unit 30.

The control unit 8 (FIG. 2) contains a null indicator 31, an input 32 is an indicator zero, a divider 3.3 pulses frequency, a luminance gradient counter 34, an OR element 35, a switch 36

column counters, block counter switch 37, memory sample switch 38, clock signal switch 39, block number counter 40, read generator 41, first column counter 42, second column counter 43, end of line formatter 44, decoder 45 number of blocks, the decoder 46 is the number of groups, the first and second drivers 47, 48 pulses, the counter 49 is the number of groups.

The scan control unit 10 (Fig. 3) comprises a row counter 50 switch, first and second row counters 51 and 52, a delay element 53, a display block counter 54, a counter switch 55

ten

20

40

343952.

groups, cycle switch 56, display unit row counter 57, read cycle generator 58.

The image reproducing apparatus operates as follows.

Video signal from block 1 sources. video signals are input to VSB1 2, where they are converted into a digital video signal, which is a parallel binary code with a number of bits that is transmitted at the information output of the TDC synchronously to the signal

15 quantization The recording beat, which from the first sync output 7 of the TDC 2 enters the control unit 8. In addition, TDC 2 generates human sync pulses (XI) and horizontal sync pulses (FID), which are fed to control unit 8 and scan control unit 10.

The operation of the device for reproducing an image consists of

25 of two independent modes: the mode of recording information in the first and second blocks -4 and 5 of the memory and the mode of reading information from the first and second blocks 4 and 5 of the memory with a subsequent scan of the image on the display unit 30. Both processes are combined in time, i.e., in one memory block, for example, the first one, information is recorded, from the second one - reading, and vice versa. The operation mode sets the pulse frequency divider 33, to the input of which a signal is supplied. The power pulse from the null indicator 31. The zero indicator produces pulses with a voltage frequency that feeds the display unit 30 in phase with the moments of the end of the playback frame. Denote the frequency of the signal Tact Power

thirty

35

, The phase and frequency of the power supply of the display unit 30 may not coincide with the phase and frequency of the input video signals, so a sufficient amount of time should be allotted to the recording of new information (when playing back images), but an even number of periods of the playback frame, except In addition, the frequency, power supply voltage must be greater than the critical frequency of the flicker. The 33 pulse frequency divider generates control signals for the switches: Direct counting, Count down, Read / write, Write / read siv - and sig

Control of TDCs 2 Frame change. Signals Forward and Reverse are interconverted type of square wave with frequency, Signals of Read / write and Record / read interconverted type of square wave with

frequency ---,,

4 tp

etc. at

depending on the number of periods of the playback frame allocated for recording new information. Signal change of the frame can be short pulses or a signal like a square wave with a frequency

 - f 2

4 tp

etc.

I specify 15 4 memories, etc. The switching of the 40 block number counter occurs after the information has been recorded in the last cell of the first row of the first memory block 4 at the trailing edge of the signal at the moment the first or

second memory unit to receive new

information.

Suppose that the information bit of the first counter 42 of the column 42 is recorded in the first memory block 4. A call that through the switch 37

this signal Read / write has a block counter input to

+1 counter 40 number of blocks. In addition, there is an overflow of a counter of 42. columns. The recording of information continues into the first line of the first memory block 4 of the second of the M information conversion blocks 3ij. After recording the latest information

level

h

 o, and the write / read signal is 1. The IHD through the switch 36 column counters is fed to the R input of the first counter of 42 columns and zeroed it at the corresponding points in time. FID, also reset the 40 block number counter. XI has embraced

the counter 49 is the number of groups and through the comm cell of the first row the next one is a thin SSI 50 row counters — the first one has wrapped the first counter of 42 columns, the counter of 51 rows. Thus, in the counter 40 the number of blocks and through the com- plete point in time the first counter-mutator 50 arriving at input +1, a chick of 42 columns and the first counter 51 transfers the first counter 51 rows in rows to the state 00 ... O, ,, 5 next, state, thereby selecting the second lines of the first block 4

than the first cell (5 bis-stable bits) is selected from the first row of the first memory block 4 of one of the IfeN information conversion blocks 3ij. The counter 40 of the number of blocks and the counter 49 of the number of TSW groups are already in the initial state 00 ... O. At the same time, the first outputs of the decoders 45 and 46 are level 1 (on the rest -), which is shown on the first outputs ( Q1 and HI) of the corresponding output groups of the switch 38 of the memory sample, allowing the recording of information in the first memory block 4

memory for recording information (the first FID does not cause a status change of the first counter of 51 rows, since

40 at this time, the R-input of this counter is affected by the CSI, keeping it in its initial state). Information is recorded in the second lines of the first blocks of the 4 memory of the M blocks.

45 31, j conversion information 11; ii. After the information has been recorded in the last lines of the th th DID, the first counter of the 51 rows overflows and it takes over, while the rear

the first of the M blocks 3ij transforms the gQ front of the signal of the last bit of information. The signal Clock recording through the switch 39 clock signals fed to the input of the first imaging unit 47 pulses, triggering its leading edge. The first form-gg bira thus the following first pulse generator 47 generates a memory block 4 for recording information of the pulse of the recording signal, arriving at, etc. Before writing information to the first control inputs of the first block, 4 blocks of 5 memories of all MxN blocks of 3ij mi. Thus, the information, the conversion of information. After a predetermined counter through the switch 55, the group counter enters the +1 of the counter 49 of the number of groups, transferring it to the next state and presently present at the information input of the TDC, is written into the first cell of the first memory block 4 of the first row of the first M blocks 31j information conversion. On the falling edge of the signal Tact record, coming through the switch 36 column counters to the input +1

the first column counter 42, this counter is switched to the next state 0 ... 01, and the described process is repeated, but for the second cell of the first block

4 memories, etc. The switching of the block number counter 40 occurs after the information has been recorded in the last cell of the first row of the first memory block 4 at the falling edge of the last frame signal for recording information (the first FID does not cause a change in the status of the first counter of 51 rows, since

at this time, the R input of this counter is affected by the XI, keeping it in its initial state). Information is recorded in the second lines of the first blocks of the 4 memory of the M blocks.

31, j conversion information 11; ii. After the information has been recorded in the last lines of the th th DID, the first counter of the 51 rows overflows and it takes over, while the rear

the front of the last bit signal is thus the next first 4 memory blocks for recording information, etc. prior to recording information in the first blocks 5 of the memory of all MxN blocks 3ij of information conversion. After a predetermined counter through the switch 55, the group counter enters the +1 of the counter 49 of the number of groups, transferring it to the next state and writing out the information to the last cell, the recording of information ends.

After the change signal of the frame -VTsP 2 forms, the next frame of information that is written into the second memory block 5, since at the time of the signal the change of frame the levels of the signals are switched.

record on,

, and Writing / reading to O. -The recording of information in the second memory block 5 occurs in the same way as the data recording in the first memory block 4.. In this case, the second counter of 43 columns is functioning, the second counter is of 52 rows, the second driver is 48 pulses, and the switchboard. After switching the read / write signals to 1, and Write / read to O, the null indicator. 31 generates the next pulse of the power signal Tact pulse, which leads to the generation of the Frame change signal. According to the signal, the Power Pulse counter 34 of the luminance gradations is reset to 11 ..,. Since the signal arrives at its S-in, the Forward Signal has a level of 1, and the Countdown signal is O. The first counter of 42 columns, the first row counter 51 and the row counter 57 of the display unit are zeroed, being set to the state 00 ... O.

Along the trailing edge of the power supply clock signal, the process of reading information from the first, b.p. 5 memory and image sweep in display unit 30 is started. Information is read simultaneously and synchronously from. of all blocks 4 of memory, as at the time of the end of the Tact signal, power on the first (Q1, Q2, ..., o, QM) and second (HI, H2, ... HN) output groups of the memory sampling switch 38 is set to level 1 enabling the operating mode for all the first 4 blocks of memory. The first pulse shaper 47 is in the enable state of the operation mode of reading information from the first and second memory blocks 4 and 5. Then at the initial moment of time at the output of the first memory block 4 there is information of the first cells of the first rows, which

comes to the corresponding information in the initial state, i.e. Selected the the inputs of block 13-decoding, the first lines of block 30 are displayed as control inputs of which are present, the trigger pulse is allocated the code of the highest gradation of the p-on first outputs 26 of the sweep, bones 11, ..., coming from this excites those 34 counts of brightness. At the output of decoding unit 13, 1 is allocated if the code is informational. inputs match the code on the inputs

control, and Oh, if not the same. So, during the first read cycle, the highest luminance codes are allocated. According to the signals of the read clock, the information reading oscillator 41 (1 or O) is written into the output register block 20, which consists of. from the t-bit shift register and the t-bit parallel register, i.e. the information is first accumulated. in the t-bit of the shift register 1; the first shift, according to the signal Tact. readout. With each signal Read Clock, the first counter of 42 columns increases its state by

1, select the next cell in the first row of the first memory block 4. After selecting the last cell of the first row, an overflow occurs, i.e. self-zeroing of the first counter 42

columns. At the same time, the leading edge of the signal of the last bit of this counter through the switch 36 column counters is fed to the input of the form. Body 44 of the line end signal, which produces a pulse signal. End of line, overwriting information from the shift registers in parallel, i.e. information about the cells of the first-line of the display unit 30 to be excited — appears at the outputs of the block 20 of the output registers. Signal End of the line through the switch 50 line counters are switched

The first counter is 51 rows in the next state, in which the second rows of the first memory block 4 are selected for reading information. Signal The end of the line is fed to the input of the delay element 53, which triggers the trailing edge of the signal. The delay element 53 generates a trigger pulse of the required duration for

display cells, which is fed to the clock input of the scanner unit 26, which is clocked decoders. Since the counter of 57 lines of display units still finds

 the output lines of the display unit 30, for which in the first memory block 4 the code 11 ... 1 of the highest luminance gradient was stored. The falling edge of the start pulse from the output of the delay element 53 through the switch 54 of the row of display units enters the input +1 of the counter 57 rows of blocks zhenin and translates it into the next state 0 ..- 01, i.e. the switching of the counter 57 lines of the display unit 30 is delayed by the time required for starting the cells of the display unit 30.

The described process is repeated for the following second lines of the first memory block 5 and the display block 30, etc. before running the last line of display 6jfoKa 30 cells. After that, overflow occurs, i.e. self-zeroing of the counter 57 lines of the display unit (self-zeroing of the first counter of 51 lines occurs before starting the cells of the last lines), and the falling edge of the signal of the direct output of the last bit of the counter 57 lines of display blocks through the switch. A cycle 56 starts the read cycle generator 58. The latter produces a pulse, the duration of which determines the delay of each subsequent read cycle relative to the previous one. The impulse of the generator 58 of the loop of the state, arriving at the input -1 of the counter 34 gradations of brightness, translates it into the state 1 .., 10, setting the next gradation of brightness. During the pulse operation of the read cycle generator 58, the first column counter 42 and the first row counter 51, as well as the row counter 57 of the display blocks by acting on the R inputs through the respective switches, are kept in their original state. At the end of the impulse, a new cycle of interconnection takes place already for the next gradation of brightness. In total, K-1 read cycles occur during the playback frame period, since it does not make sense to reproduce the last luminance gradient (code 00 ... O).

Next signal Tact Power

signal level Direct counting changes- 55 Digital converters, and the second, from O to O, and the signal level Reverse is the third and fourth outputs of the unit

the count is by 1. Similar read cycles occur, only in this case the first counter is 51 lines

These are connected respectively to the first address input of the first information conversion unit, which

0

five

0

five

0

and the 57 line counter of the display units is set to the initial state 11 ... 1 by acting on the S-inputs of the signal Read cycle. And the signals End of the line and the start pulse of the delay element 53 through the corresponding switches are fed to the inputs -1 of the specified counters, i.e. There is an information output on the last lines of the first memory block 5 and an information scan in the display block 30, too, from the last lines to the first. Shaper 58 of the read cycle is triggered in this case by an inverse output signal of the last digit of the counter 57 lines of the display unit.

The device operates similarly when reading information from the second memory block 5 after the corresponding switching of control signals.

It is advisable to execute each cell of the display unit on the basis of a thyristor optocoupler, with a load to turn on the light emitting element, and connect the LED of the optocoupler to the corresponding inputs of the column and row of the display unit.

Claims (1)

Invention Formula A device for reproducing an image, comprising a control unit and serially connected block of video signal sources, a video digital converter and a first information conversion unit, containing first and second memory blocks, the outputs of which through the serially connected decoding unit, the control input of which is the first control input the information conversion unit, and the output register unit are connected to the information input of the display unit, the control input of which is connected to Exit scanner, wherein the first and second sinhrovyhody video digital converter connected to the first and second inputs of the control unit, a first output connected to a control input of the video Digital converter, and the second, third and fourth outputs of the block These are connected respectively to the first address input of the first information conversion unit, which is the first address input of its first storage unit, with the second address input of the first information conversion unit which is the first address input of its second storage unit and with the first control input of the first information conversion unit, characterized in that quality of the reproduced image, the scan control unit and (MxN-1 / information conversion units) are additionally inserted into it, the second synchronized output of the video-digital converter is connected to the first input of the control unit and a scan, the second input of which is connected to the third input of the control unit and the third output of the video-digital converter, the second, third and fourth outputs of the control unit are connected respectively to the first address input, the second address input and the first control input of the input information conversion units, the fifth and The sixth outputs of the control unit are connected respectively to the second control inputs of the information conversion units, which are the control inputs of the first blocks of the pagm. information development and with the third control inputs of information conversion units, which are the control inputs of the second memory blocks of information conversion blocks, the seventh output of the control unit is connected to the third input of the scan control unit, the eighth output of the control unit of memory blocks of conversion blocks connected to the first clock input information. five information conversion units, which is the clock input of the output registers block, the ninth output is a block. As the control is connected to the fourth input of the scan control unit and the rewrite input of the information conversion blocks, which is the rewrite input of the output registers block, the tenth output of the control block is connected to. the fifth input of the sweep control unit, the first, second and third outputs of which are connected respectively to the second clock input of the information conversion units, which is the clock input of the scanner, to the fourth and fifth inputs of the control unit, fourth, fifth and sixth outputs of the control unit sweep are connected respectively to the fourth control inputs of the information conversion units, which are the inputs of the scanning units of the information conversion units, with the third address inputs of the blocks information generation, which are second address inputs of the first memory blocks of information conversion blocks, with fourth address inputs of information conversion blocks, which are second address inputs of the second memory blocks of information conversion blocks, and the information output of the video digital converter is connected to information inputs ( MxN-l) -x information conversion units, which are the information inputs of the first and second 0 0 five fg „JtiKm cvi rb / daw 32 S - g 35t Q1 S3 C2 D2 Q3 HI Q End of 21 spurs ML 15 f W five xi R 3 iiS Sh 33 32 "7 Jj Cuurn cycle - banii 22 J-, „Cvt / jbffa / ff / eJ3anaci 1B 3anu (lct / uJbf8a ffe right ct / em H OSH) Good77 „CMeffaf cfdpo J FIG. 2 9CCI 11xi ii nonets 2 / fWW C5 ZCV 2Zcv (j & ieOfAf V i-r 51 e 55 2if f / 52 23 „(/ §Aw§ / record „Record icti / i / n / §OHue tf oi pofm & fff cvem one 53 t -eleven Editor I.Rybchenko Compiled by E. Borisov Tehred L. Oliynyk Order 3982/58. Circulation 638 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 5s 58 23 7 Proofreader V. But ha