SU1256245A1 - Device for converting small-frame television standard signal - Google Patents

Abstract

The invention can be used to interface the scan rate of small-frame systems with the scan rate of broadcast television systems and provides a reduction in power consumption. The video signal passes through the A / D converter 1 and is recorded by the signals of the recording mode control unit 6 in the first buffer memory unit 2 (FBT). In this block, a temporary decompression of the signal takes place, which is fed to the block 3 of the RAM. The decompressed digital signal is derived from BOI 3 in accordance with the target codes generated by the unit 7 to generate the address codes, and entered into the second BBU 4. In this block, a temporary compression occurs in order to form the video signal in accordance with the broadcast standard. From the second UPS 4, video is read by signals from the read mode control block 8 (feuTjaf (L

Description

signal, which through TsA11 5 goes to the output. Using the signal generation unit 12 of the inversion signal, the element OR 13, the trigger 11 and the signal generation unit 10, the Invention relates to a television technique and can be used to interface the scan speed of small frames of systems with the scan speed of broadcast television systems.

The purpose of the invention is to reduce power consumption.

Fig. 1 shows the structural electrical circuit of the device for converting the small-frame television standard in Fig. 2 — the structural electrical circuit of the first block of the buffer memory in Fig. 3 is the structural electrical circuit of the recording mode control unit in Fig. 4 - the structural electrical circuit of the control unit of reading mode Fig. 5 shows the structural electrical circuit of the sampling signal forming unit J in Fig. 6; the structural electrical circuit of the generating unit of the address codes in Fig. 7 is structural electrical Single block diagram form handling signals; Fig. 8 shows the waveform of sampling rows and columns in the paged mode of the random access memory of the memory block of Fig. 9, depending on the frequency of the memory management clock signals in Figs. 10 and 11 are temporary 12 shows the timing of the operation of the sampling signal forming unit.

A device for converting a small-frame television standard contains an analog-to-digital converter 1, a first block 2 of buffer memory, a block 3 of RAM, a second block 4 of buffer memory, a diffro-analog converter 5,

KI is set to the BOP 3 mode of operation or the element-level sampling mode. The synchronization unit 9 ensures the coordinated operation of the device units. 12 il.

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a write mode control unit 6, an address code generating unit 7, a read mode control unit 8, a synchronization unit 9, a sampling signal generating unit 10, a trigger 115, a conversion signal generating unit 12, and an OR element 13.

The buffer memory unit 2 is executed on the basis of series-parallel shift registers 14 and parallel registers 15 (FIG. 2). The recording mode control unit 6 is made, for example, on the basis of a multi-bit binary counter 16 with the initial installation of the code, the element OR NOT 17, the elements 18 and 19, the trigger 20, the multivibrator 21 and the switch 22 (FIG. 3). The read mode control unit 8 is made, for example, on the basis of multi-bit binary account-r; 23 and 24 with the initial installation of the code, multivibrators 25 and 26, the decoder 27 and the trigger 28, for example, 1K-type (figure 4).

The sampling signal generating unit 10 is made, for example, on the basis of a m: multidisciplinary binary counter 29 with the initial installation of a code, a clock pulse generator 30 and a programmable logic array 31 (FIG. 5).

The address code generation unit 5, for example, based on multi-bit binary write and read counters 32 and 33 with the initial installation of the code, switch 34, elements 35 and 36, multivibrator 37 and element 38 (fig.6),

The inversion signal generating unit 12 is made, for example, on the basis of the first 39J of the second 40, third 41, and fourth 42 triggers, for example, the first 43, second 44, and third 45 And elements and OR 46 (Fig. 7).

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The device works as follows.

In the analog-digital converter 1, the video signal is converted into its digital form. From the output of the analog-to-digital converter 1, the digital video signal is fed to the first input of the first block 2 of the buffer memory, where it is temporarily expanded to record the decompressed video signal coming from the output of the first block 2 of the buffer memory to the input of the main memory block 3. The read video signal from the output of the RAM block 3 is fed to the first input of the second block 4 of the buffer block 1, where it is temporarily compacted to form a video signal in accordance with a broadcasting standard or close to it. From the output of the second block of buffer memory, the digital video signal is fed to the input of the diffraction analogue converter 5, where it is converted into analog form and then goes to the output of the device. The presence in the device of two blocks of buffer memory at the input and output of the RAM block 3 allows simultaneous recording and reading of video signals with different image decomposition standards, as well as harmonizing the relatively low access frequencies of the dynamic RAM memory of the RAM block 3 high sampling rate of the output video signal of a broadcasting standard or close to it.

The video signal of the input image decomposition standard is recorded as follows.

The samples of the input video signal in the form of n-bit words (usually PB8) come from the output of the analog-digital converter 1 to the information inputs of the n serial-parallel shift registers 14. The bit width of the serial-parallel shift registers 14 and parallel registers 15 is selected equal to parallel-sequential registers of the second block 4 of the buffer memory. The recording of the input video signal samples in the series-parallel registers 14 is carried out according to post 2445.

impulses to their clock inputs whose frequency corresponds to the sampling rate of the input video signal. The set of clock pulses that determine the structure of samples within the forward strokes of rows and frame of the recorded image and fed to the clock inputs of the series-parallel shift registers

14 is formed with the aid of element 18, at the first input of which a mixture of lowercase and frame fading pulses of negative polarity is fed, and at the second input enters

a continuous sequence of pulses with a sampling frequency of the input video signal, phase-linked to horizontal damping pulses. A mixture of lowercase and personnel extinguishing

recording pulses are formed using the element OR-NOT 17, to the first and second inputs of which frame and line damping recording pulses of positive polarity are applied, respectively. At the moment of complete

filling serial-parallel registers 14; their contents are rewritten into parallel registers.

15, to the clock inputs of which it supplies, with a rewriting signal. The overwrite signal comes from the high bit of counter 16, the counting coefficient of which corresponds to the size of the registers of the first block 2 of the buffer memory.

During the return stroke of the write lines, the counter 16 is set to the zero state by applying to its control input a setting of the initial code of the lower-case quenching write pulse. In

the forward stroke time of the write lines; the counter 16 changes its state synchronously with the filling of the series-parallel shift registers 14. The rewriting signal is formed

at the output of the older bit of the counter

16, in addition, is fed to the input of the multivibrator 21, where a pulse of a request for a write cycle is formed, which is fed through the switch 22

to the first input of the inversion signal generating unit 12. As a result, in the write cycle, the contents of the parallel registers 15 are recorded in the RAM block 3 by the address code

records produced in block 7 of the formation of address codes.

The write address codes are generated using a 32 write address counter, which is set to the zero state when its initial control code of a frame damping pulse is applied to its control input. The counting of Counter 32 is changed by one at the end of each recording cycle, the pulse of the address change arriving at the first input of the And 35 element, to the second input of which, during the writing cycle, the logical 1 arrives.

As a result, a rewrite pulse from the output of the element 35 is applied to the clock input of the counter 32 of the recording addresses, while the output address code for the next write cycle is set at the outputs of the bits of the counter 32. From the outputs of the counter bits of the 32 write addresses through the switch 34, the write address codes are sent to the second: erasure of the block 3 RAM. The communica- tion of the write and read address codes is effected by applying a write cycle signal to the second control input of the switch 34 (FIG. 11 e).

Video signal reading: a with the image decomposition output standard is performed as follows.

The samples of the output decompressed video signal from the output of the RAM block 3 are fed to the first input of the second block 4 of the buffer memory. Shift clock pulses with a sampling rate of the output video signal, i.e. for a broadcast standard equal to 13.5 MHz, are supplied to the clock inputs of the parallel-serial shift registers of the second block 4 of the buffer memory from the first output of the block 9 of synchronization.

 Conversion of parallel-sequential registers of the second block 4 of the buffer memory into the mode of parallel input of samples of the decompressed video signal is performed according to the signal received from the output of the decoder .27 of the block 8 of the control of the read mode. In order to form this signal, the lower order synchronization pulses of the broadcast standard from the second output of the synchronization unit 9 are fed to the control input of the installation of the initial code of the counter 24 and the input of the installation of the trigger 28. In this case, the counter 24 is zeroed out, and the level of logic 1 is set at the output of the trigger 28. At the clock input of the counter 24, the frequency of the sampling frequency of one video signal is given. Coef

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The counting counter of the counter 24 is selected in such a way that the positive differential signal of the higher bit of the counter 24 arriving at the counting input of the trigger 28 sets at the output of the trigger 28 a logic level

About to the beginning of the active part of the output sweep line. As a result on

trigger output 28 produces positive polarity pulses, the leading edges of which coincide with the beginning of horizontal synchronizing pulses, and the falling edges advance the beginning of the active part of the lines by a time sufficient to perform the decompressed video reading cycle from the RAM block 3 to the second buffer memory block 4 .

The signal from the output of the trigger 28 zeroes the counter 23, arriving at its control input of the initial code setting, and the clock input of the counter 23 is fed I1 1 pulses of the video signal sampling frequency. The counting coefficient of counter 23 corresponds to the register size of the second, block 4 buffer memory, which should be sufficient so that at the maximum sampling frequency of the output video signal, the output period of the second block 4 of the buffer memory to the device output is enough to execute two memory sampling cycles for example, a write cycle and a read cycle Thus, at the output of the decoder 27, a signal with a duration of one sampling period is formed, periodically shifting the parallel-serial shift registers of the second buffer memory unit 4 to the parallel input mode.

The first entry of the decompressed i video signal is made at the moment of starting the active part of the line. Each recording of a decompressed video signal into the second block 4 of the buffer memory is preceded by the generation of a read cycle request pulse, which is ahead of the recording time by the time required to generate memory management clock signals providing the readable video signal at the output of the operational memory 3 to the recording moment. A read cycle request pulse is generated using a multivibrator 26, the input of which is connected to the output of the corresponding bit of counter 23.

The decompressed video signal is read from the RAM block 3 in accordance with the address read codes generated in the read address counter 33 of the address codes generating block 7. Since the broadcast standard provides for interlaced image decomposition, the read address counter 33 has two initial states. In the first field of the read frame, the counter 33 of the read address is nullified by the damping field impulse coming from the third output of the synchronization unit 9 to the control input of setting the initial code of the counter 33, and by the field recognition signal coming from the fourth output of the synchronizing unit 9 to the corresponding bits of the information input of the parallel installation of the counter code 33. The identification signal of the duty cycle equal to two has a negative polarity in the first field and a positive polarity in the second field, and The field recognition signal is switched in phase with damped field pulses. As a result, according to the damping pulse of the second field at the outputs, the rows of the counter 33 establish the initial address code of the second field. Thus, in the array of memory cells of the RAM unit 3, areas are formed that are separately addressed in the first and second fields of the frame of the read image.

The read address codes are changed with the arrival of a change of address pulse arriving at the first input of the I 36 element and then to the clock input of the counter 33. The passage of the address change pulse through the And 36 element is allowed only in read cycles. For this, the signal of the write cycle is inverted on the element 38 to the second input of the element 36. During read cycles, the address codes from the bits of the counter 33 of the address of the link are sent through the switch 34 to the address inputs of the RAM 3. Thus, a continuous reading of the video signal is provided at the output of the proposed device.

in accordance with a broadcasting standard or close to it.

The processes of recording the input and reading out the output video signals with temporal decomposition and compaction are provided by the adequate formation of clock signals for controlling the operational memory of the dynamic type of the operational memory unit 3. The memory sampling mode begins with the arrival at the pulse-reversal signal generating unit 12 of a request for a write cycle and a read cycle.

Consider first the execution of read cycles, whose frequency in the low-frame-rate television standard converter is substantially higher than the frequency of write cycles.

The impulse of the request for the loop of the loop (Fig. 10a) is fed to the installation input of the trigger 39 of the reverse signal generating unit 12. In this case, at the direct output of the flip-flop 39, the logic level 1 is set (FIG. 10c). On the direct outputs of the remaining triggers 40-42, a logic level O is maintained (FIG. 10 g and 3). Since in this case, the output signal element And 43 signal recording positive polarity is missing (figure 10 e). That switch 34 in the address code generation unit 7 passes the address read codes to the address inputs of the RAM block 3, and AND 36 opens to pass the read address change pulse.

The positive-polarity read cycle signal from the direct output of the flip-flop 39 is fed to the first input of the element OR 46, the output signal (figure 10) of which is fed to the gate input of the clock pulse generator 30 and to the control input of setting the initial code of the counter 29 of the forming unit 10 sampling signals. In the absence of a signal (Fig. 10 d), the counter 29 is in the zero state, and the clock pulse generator 30 is turned off. With the arrival of the signal (Fig. 10 d), a clock pulse generator 30 is excited, from the output of which the clock pulses arrive at the clock input of the counter 29, which begins to change its state. The outputs of the bits of the counter 29 are input variables

for a programmable logic array 31. The output variables are memory control clocks, i.e. row sampling signal (fig. 12a), column sampling signal (fig. 12 b) and recording signal (fig. 12 to incoming); to the control input of the main memory unit 3. Vcod variable are also commutation mutation pulses address codes (Fig. 12 g) coming from the first output of the sampling signal generating unit 10 to the first control input of the switch 34. The lower and higher bits of the address code in the sampling cycle for pushing the address code are switched by this signal required for operational storage devices with multiplexing

by address. I

The output variable of the programmable logic matrix 31 are also address change pulses (Fig. 12 that come from the second output of the sampling unit 10 to the first inputs of And 35 and 36 elements of the address code generating unit 7. The address change pulses (Fig. 12 d) are generated then, according to the signals of row sampling (Fig. 12a) and column sampling (Fig. 12b), the adress code of the current sampling cycle is already fixed in the internal address registers of the operational storage of the operational memory unit 3 and the address change in the 7 form block Addressing codes does not entail distortion of the video signal being coupled. The last output variable is from the sampling cycle end pulses (FIG. 12 e) coming from the fourth output of the signal conditioning unit 10 to the third input of the reverse signaling unit 12. Since the second and third inputs of the element 44 and there is a logic level 1, then the end signal of the sampling cycle (Fig. 12e) passes through the element 44 and 44 to the counting input of the trigger 39 and overturns it; H This sampling cycle ends. Thus, the duration of the sampling cycle is determined by e from the receipt of a request for a read cycle to the pulse reversal signal generating unit 12 until the trigger 39 returns to its initial state. The duration of the sampling cycle can be adjusted by changing the generator frequency to 30 clock pulses.

In addition to the indicated output signals of the counter bits 29, the input variables of the programmable logic array 31 are also the write cycle signal (FIGS. 10 and 11 e) and the page mode interrupt signal (FIG. 12 g), respectively, to the second and first inputs of the generation unit 10. sampling signals. If there is a recording cycle signal (Fig. 11 e), a write signal is generated at the output of the programmable logic array 31 (Fig. 12 into the incoming memory unit 3. The paging mode interrupt signal (Fig. 12 g) is intended for transferring the operative memory of the unit 3 of the operating memory from the page mode to the element-by-element sampling mode. In this video signal reading mode, the first pulse of the request for a read cycle before the start of the active part of the line trigger 11 is tilted and is set to exit at its output. ivaets logical level O, i.e. set page mode random access memory, in this mode selection signal lines (12 a) receives the logic level 0, thereby fixing the row address into the RAM unit 3 is RAM memory.

In subsequent requests for a read cycle in the sampling signal generation unit 10, only a column select signal (FIG. 12 b) is generated, which records the address code of the read columns that change in the read address counter. In the page sampling mode, the power consumption of the RAM 3 is determined by the value (FIG. 9 b), and the timing diagrams of the row and column sampling signals are presented respectively in Fig. 8 a and b. The end of the page mode occurs when the trigger 11 is switched to the initial state by a signal from the output of the element OR 13, which enters the input of the trigger 11.

The duration of the page mode operative storage devices

II

limited by the maximum duration of the row sampling signal

10 MCS, on the one hand, and the need to perform automatic regeneration of the contents of memory RAM unit 3 on the other hand. Since the regeneration is performed by enumerating the addresses of the lines, during the period of regeneration of the operative memory devices (Tre 2 µs) it is necessary to refer to all the lines.

16K and at least 8-9 addresses of 64K random-access memory storage lines. This means that, taking into account the limitation on the duration of the row sampling signal, the optimal continuous reading cycle duration for the group of samples (Fig. 8) will be 7-8 MCS. Such periods are generated by the read address counter 33 and the multivibrator 37 ,. the input of which is connected to the output of the corresponding bit of the counter 33. The signal from the output of the multivibrator 37 is fed to the input of the element OR 13 and then to the input of the trigger 11, tilting it. The page mode is terminated, the row selection signal assumes the level of logical 1. However, with the arrival of the next request pulse for the read cycle, the trigger

11 the page mode is tilted back and restored, in the read mode the reduced power consumption and automatic regeneration of the contents of the RAM unit 3 is provided.

The video input signal is recorded as follows.

During the horizontal damping pulse of the broadcast standard, when there are no read cycle request pulses (FIG. 10 b), the switch 22 transmits the write cycle request pulses directly from the output of the multivibrator 21, which is provided by feeding the control input 22 of the switch trigger 28. At the forward run of the line, when there are request pulses for both a loop and asynchronous with them for a write cycle, the pulses are generated

5624512

request for a write cycle, time-bound to regularly formed requests for a read cycle request. In this case, the Pulse of request 5 for the write cycle is fed to the second setup input of the trigger 20 and flips it, opening the AND 19 element for the passage of a pulse generated using a multivibrator

10 25, the temporary position of which corresponds to 11 b. On the forward run of the row, this pulse passes through the switch 22 and is the impulse of the request for a write cycle that

15 provides conflict-free alternate generation of memory access signals. The impulse of request for a write cycle generated in such a way goes to the setup

20 trigger input 40.

During the horizontal damping pulse, when there are no read cycle request pulses, the operation of the processing signal generation unit 12 corresponds to FIG. 10, except that the read cycle signal (figure 10c) is absent, and a similar write cycle signal at forward trigger output

0 40 (FIG. 10 g) and at the output of the element E 43. On the forward run of the line, the operation mode of the conversion signal generating unit 12 is represented by the diagrams in FIG. The execution of the sampling cycle on the request pulse for the read cycle (Fig. 11 a) occurs in the same way as described.

With the arrival of the request for a write cycle, the trigger 40 overturns with (11 g). The signal from the inverse output of trigger 40 overturns trigger 42, since at its I and K-in: k there is a logical 1 coming from the direct output of trigger 39, and at the forward output of trigger 42 a pulse appears (Fig. 11); which defines the end of the paging read mode to allow access to the memory in one write cycle. The signal from the inverse output of the trigger 42 closes the element 45 to prevent the trigger 40 from tipping over the first pulse of the end of the sampling cycle (Fig. 11 g). On this impulse, only the flip-flops 39 and 42 (Fig. 11c) tilt from this moment at the output of the AND 43 element, a signal of the write cycle is formed, and at the output

131

The element IL 46 still remains, the signal (Fig. 11 d) traversing the memory.

After the end of the write cycle in the memory by the second pulse of the end of the sampling cycle (Fig. 11 g), the trigger 40 returns to its initial state, and the pulse from the output of the element I 45 (Fig. 10 and 11 and 11) returns the trigger 20 of the mode control block 6 records Thus, during the horizontal damping pulses of the broadcast standard, the write cycle in the RAM block 3 is fired at the moment the pulse of the request for the write cycle arrives at the conversion signal generating unit 12, and on the forward run of the line the write cycle is interrupted readout mode (Fig. 12), providing the power consumption characteristic of the RAM unit 3 corresponding to the proposed device (Fig. 9c) as compared with the well-known: (Fig. 9a).

Claims (1)

Invention Formula A device for converting a small-frame television standard, containing a series-connected analog-to-digital converter, a first block of buffer memory and a block of RAM, the second input of which is connected to the first output of the address code generation unit, the first input of which is combined with the first input of the recording mode control unit and is a sync signal input of the device, a digital-analog converter and a read mode control unit, the first and second outputs of which are connected respectively About to the second and third inputs of the recording mode control unit, the first and second outputs of which are connected respectively to the second and third inputs of the first block of the buffer memory, and the input of the analogue digital converter and the output of the 1Ц1фроа.alalog converter in 5624514 These are, respectively, the input and output of the device, differing from the fact that, in order to reduce power consumption, a second block of buffer memory is inserted in it, connected between the output of the RAM and the input of the D / A converter, second and third inputs of the second buffer memory block 0 are connected respectively to the third output and the first input of the read mode control unit, the reverse signal generation unit, the OR element, the trigger and the signal formation unit 5 sample cards connected in series between the third output of the write mode control unit and the synchronization unit first 0 and the second outputs of which are connected respectively to the first and second inputs of the control unit of the read mode, and the third and fourth outputs of the synchronization block are among 5 yen respectively with the second and third inputs of the address code generation unit, the fourth and fifth inputs of which are connected respectively to the second and third exits 0 signal conditioning unit 35 40 45 ki, the second input of which is combined with the sixth input of the address code generation unit and connected to the second output of the conversion signal generating unit, while the fourth output of the reading mode control unit is connected to the second trigger input and to the second input of the conversion signal generating unit, the third input and the third output which are connected respectively to the fourth output and the third input of the sampling signal generating unit, the fourth output of the conversion signal generating unit is connected to the fourth input of the control unit neither the recording mode, and the second output of the block forming address codes is connected to the second input of the OR element. 6} (0d1 6; foff2 77 BJTodJ FIG. 2 7s / ff djroffe Bwds 21 22 Bjfod4 / V Su / jroc J WY} r0 1 " 3 & / jfO J FIG. eight SU / Tsuma cvu / 776 / ea-l uM records neither J t L Jl Jl FIG. 12 Compiled by A. Prozorovsky Editor I. Shulla Tehred M. Khodanich Proofreader I. Muske Order 4838/59. Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Physical C (CV (// 776fScr U S t. Jl Jl Jl Lt