SU1334310A1 - Device for controlling transistors of push-pull converter - Google Patents

Abstract

The invention relates to electrical engineering and can be used to balance the reversal mode of an output transformer in two-stroke transistor converters of secondary power sources. The aim of the invention is to increase the reliability of KPD and enhancement of functionality. Due to the introduction of the conductor 20 duration of the conducting state of the second transistor 2, the maximum duration of the conducting state of transistor 1 is limited by a certain amount compared to the maximum possible duration of the conducting state of transistor 2, thereby balancing the switching of the transformer 5 regardless of the reasons capable of causing asymmetry,. both in regulated and unregulated converters, which increases the reliability of the efficiency and expands the functionality of the device. 2 Il. i (L s

Description

113

This invention relates to electro. technology and can be used to balance the reversal mode of the output transformer in two-stroke, transistor converters of secondary power sources.

The purpose of the invention is to increase the reliability of efficiency and expansion of functionality.

FIG. 1 shows the structure of the device; Fig. 2 shows time diagrams of voltages at the corresponding circuit elements.

A device for controlling transistors 1 and 2 of a push-pull converter 3 feeding from source 4 with an output transformer 5, the secondary winding of which is connected via a rectifier 6 and filter 7 to a load 8, contains a master oscillator 9, the clock output of which is connected to the driver input 10 protective pauses and a counting input of the trigger 11, the direct and inverse outputs of which are connected to the first inputs of the first 12 and second 13 elements of the I, respectively, the outputs of which are connected to the bases of the first 1 and second 2, respectively, converter 3. The output of the sawtooth voltage of the generator 9 is connected to the inverting input of the first comparator 14, the direct input of which is connected to the EXH: the differential amplifier 15, the inverting input of which is connected to the load 8, and the direct source 16 reference voltage. The second inputs of elements 12 and 13 are connected to the output of the imaging unit 10, the third input of element 12 is connected to the output of the first comparator 14, and the third input of element 13 to the output of the second comparator 17, the direct and inverting inputs of which are connected to the outer plates of two series-connected the capacitors 18 and 19 of the formers 20 of the duration of the conducting state of the second transistor 2. The shaper 20 also consists of OR-NOT elements 21 and 22, bit cells 23 and 24 and a variable resistor 25, the average output of which is connected to the dates ICU 26

current converter 3, one extreme

The OUTPUT is connected to the direct input of the comparator 17 and the switched input of the key 23, the output of which, together with the output of the key 24, is connected to the point

102

the capacitor plates 18 and 19 are connected to the common bus, and the control input is connected to the output of the element 21, whose inputs together with the corresponding inputs of the element 22 are connected to the output of the driver 10 and the inverse output of the trigger 11. The output of the element 22 is connected to the control Key 24, the switching input of which is connected to the inverting input of the comparator 17 and the output of the analog switch 27, whose switching input is connected to another output of the resistor 25, and the control input to the output of the element 12, the fourth input of which is li ne output to the clock generator 9, the forming voltage with a duration of a pause,.

The device works as follows.

First consider the operation of the device when the control voltage value is less than the maximum sawtooth voltage of the master oscillator 9.

While the control signal is larger than the sawtooth voltage, the output of the comparator 14 generates a signal 1 (Fig. 2e), which is fed to an AND 12 logic element, to the other inputs of which a signal C of the trigger 11 and a driver 10 is applied. The element 12 generates a signal (FIG. 2e), which is supplied to turn on the transistor 1. At the same time, this signal at the control input switches on the analog switch 27, providing the capacitor 18 with the integration of the signal from the current sensor 26. Upon termination of the signal; 1L 1 at the output of the element 12 (turning off the transistor 1), the switch 27 is turned off and the signal storage phase from the capacitor 18 begins.

During the time interval considered above, the capacitor 19 is shunted by the bit switch 23, which receives a turn-on signal from the output of logic element 21 (Fig. 2k) at the control input, since a signal 1 is generated at the output of the comparator 17

After switching the trigger 11 and the expiration of the time fj, determined by the duration of the signal from the output of the imaging unit 10 under the influence of the signal of the actual sum of the trigger signals 11

(Fig. 2d) and the comparator 17 a pulse is generated at the output of the logic element 13, which turns on the second transistor 2. At the same time, the output switch 26 is locked from the output of the element 21 (Fig. 2k) and the integration of the signal from the current sensor 26 begins at the second cycle operation of the converter 3. As soon as the voltage on the condenser 13 reaches the value of the signal stored by the capacitor 18, the output signal of the comparator 17 becomes O. At this time, the formation of the control signal of the transistor 2 stops and Shutdown (FIG. 2h).

The integrators are restored before the formation of the next control pulse of the first transistor 1. For this, the bit switches 23 and 24 are turned on by pulses from the elements 21 (Fig. 2g) and 22 (Fig. 2k). Then the cycle is repeated.

Resistor 25 with a variable position of the tap allows you to correct the operation of the driver 20 of the control signals of the conducting state of the transistor 2. The need for correction occurs, for example, when the parameters of the capacitors 18 and 19 are scattered or the time delay of the switching delays of the first 1 and 2 second-2 transistors converter 3.

Consider the operation of the device when the control voltage from the output of the amplifier 15 exceeds the maximum value of the sawtooth signal of the generator 9.,

In this case, a signal with a level of 1 is formed at the output of the comparator 14, and a signal with a duration of, 5T - t, - 2 is output from the output of the logic element 12.

Suppose that during this time the capacitor 19 has accumulated a charge corresponding to the voltage U, which is stored during the second half-period of operation of the converter 3. When transistor 2 is turned on (by analogy with the previous case), the capacitor 19 starts accumulating charge on its plates. If the equality of the charges (and, hence, the voltages) on the capacitors 18, 19 occurs in the interval 2, the duration of the conducting state of the transistor 2

five

0 5

about c

g

0

five

ten

longer than the conductive state of transistor 1, which is a sign of balancing.

Thus, the maximum duration of the conducting state of transistor 1 is limited to a certain value compared to the maximum possible duration of the conducting state of transistor 2, which ensures balancing the remagnetization of the transformer, regardless of the causes that can cause asymmetry, both in regulated and in unregulated converters, which increases reliability, efficiency and expands the functionality of the device.

Claims (1)

Invention Formula A device for controlling two-stroke transistors, a transformer output transformer containing a master oscillator-, the output of which sawtooth voltage is connected to the inverting input of the first comparator, the direct input of which is connected to the output of the differential amplifier, the inverting input of which is connected to the load, and the direct the reference voltage source, the clock output of the Master Generator is connected to the input of the protective pause driver and the counting input of the trigger, the direct and inverse outputs of which connected to the first inputs of the first and second elements And, respectively, the outputs of which are connected to the bases of the first and second transistors of the inverter, respectively, the second inputs are connected to the output of the protective pause generator, and the third to the outputs of the first and second comparators, respectively, and the inverting input of the second comparator is connected to the output of the analog switch, the control input of which is connected to the output of the first element I, and the current sensor of the converter, characterized in that, in order to increase reliability, the efficiency expansion of functionality, it is provided with generator duration conductive state of the second transistor, formed on the AND-NO elements, NOR, two bit keys, variable resistor and two capacitors 5. 133 caropaxj with two plates interconnected with output switches and a common bus, and two other plates connected between the inverse and direct inputs of the second comparator and the switched inputs of the first and second bit, respectively, the control inputs of which are connected to the outputs elements of RSHI-NOT and AND-NOT are, respectively, inputs Phi1.2 Compiled by Zhmurov editor L. Pcholinsk Tehred M. Hodanich Proofreader V. Girn to Order 3976/54 Circulation 65 Subscription VNrdapi State Committee of the USSR for inventions and discoveries 113035, Moscow,, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Design, 4. b which are connected to the output of the protective pause driver and inverse trigger output, the variable resistor is connected between the switched inputs of the analog switch and the second bit switch, its middle output is connected to the current sensor output, and the clock output of the master oscillator is connected to the fourth input of the first element I.