SU1327312A1 - System for transmission of discrete information with intermediate storage - Google Patents

Abstract

The invention relates to communication technology and provides for the exclusion of loss of information. The system contains a packet length determining unit 1, a receiver 2, a demodulator 3, a decoder 4, a signal analyzer 5, a read signal generator 6, a memory block 7, an encoder 8, a modulator 9, a transmitter 10. A recording control block 11 is entered into the system packages. 2 Il. g (L tfJue. 1

Description

The invention relates to communication technology and can be used in packet switched communication networks.

The purpose of the invention is to eliminate loss of information.

Figure 1 shows the structural electrical circuit of the pre-set system; Fig. 2 shows embodiments of a packet length determining unit and a packet writing control unit.

The discrete information transfer system with intermediate accumulation contains a block 1 for determining the packet length, receiver 2, demodulator 3, decoder 4, signal analyzer 5, generator 6 of read signals, memory block 7, encoder 8, modulator 9, transmitter TO, packet writing control unit 11.

Block 1 for determining the packet length contains (FIG. 2) the first and second elements And 12, - 12, and 13 - 13, elements OR H - 14, generator 15 clocks, buffer registers 16, - ISg, decoders 17 - 17, duration packages, the first and second valves 18, - 18 ,, 19, - 192, elements NOT 20 | - 20.

The recording control unit 11 contains (FIG. 2) elements AND 21 - 21, 22, - 22 ,. 23 ,, - 23, 24 - 24, 25 - 25J, 26 - 26j, elements OR 27 - 27.5 elements NOT 28, - 28 ,, 29 29 ,, valves 30 „- 30 ,, 31, -.

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The system works as follows.

If one of the registers 16 - 16jj is free (Fig. 1), then through the line through the corresponding open valve 19-19, information is received and recorded in the corresponding register 163, from the first outputs of which information goes to the decoder 17, -17, j the duration of the packets (figure 2). At one of the first outputs of the corresponding decoder 17, - 17, a positive potential appears, signaling the length of the received packet, and at the second output of the decoder 17, 17 - an occupancy of the corresponding register 16 - 16, which is closed. a specific valve 1 9, - 19 2. and enters the line (register busy signaling).

The signal from the corresponding first output of the decoder 17, -17 enters the packet recording control unit 11, which distributes the information arriving at the different buffer registers 16-16, corresponding to each packet and eliminates the simultaneous recording of information from two registers. .

When a packet of length K arrives in the buffer register 16, the output of the buffer register 16 (for example, on the first) appears in a logical 1 (Fig. 2). This signal enters the elements And 21, 25, and through the valve 31i, the element NOT 29 and the control input of the valve 31-, closing

him. Thus, at the output of the valve 31i there will be a signal O, and at the output of the element is NOT 29 signal 1. Therefore, at both inputs and at the output of the element AND 25 the signal 1 turns on, which will arrive at the first input

element 12 of block 1. If the corresponding cell (not shown in figure 2) of the packet storage of this length is not occupied (the signal at the second output

element OR 27 is absent) at the second input of the first element AND 12, signal 1 will also be present. This signal will open the first valve 78, the pulses from the generator 15 will start to flow to

clock input buffer register 162 and information from the buffer register 16, through the elements And 21. , 23 and the element OR 27 will be stored in the memory.

If in the period from the beginning of the recording the information in the buffer register 16 to the end of its reading will be received a packet of similar length in the buffer register I6, j, then at its first

The output of the Wits signal, which goes to the elements. And 21, 25 and the valve 31. However, since the valve 31 is closed, the signal does not pass through it. details, valve 31 will remain open

its output will be signal 1, and the outputs of the element HE 29 and the element I 25, also O. Information from the buffer register 16 will not be read, which eliminates the possibility of information loss due to simultaneous recording. Upon completion of reading the information from register 16, signal 1 disappears at the first output of the decoder-5 torus 17, and hence at the output of the valve 31 and the control input of the valve 31. The valve 31 will open and the signal from the first output of the 17 Q decoder, (if there is also a package K in length) will go through the valve 31 to the control input of the valve 31, closing it, and preparing the elements HE / .9, - 29, And 25 - 25, 23 - 2, 27f - 27j for reading information from the buffer register 1b,

At the same time, the signal from the second output of the decoder 17 will also disappear and the second valve 19 will open, allowing writing to the buffer register 16 of the new information packet,

In memory block 7, intermediate storage of packets is carried out, with each block 7 storing packets of only one fixed gradation, from the second outputs of which signals to the second inputs indicate the presence of packets of the appropriate length to be transmitted to the communication line.

The codogram of the service signal arrives at the receiver 2 of the feedback signals. connection, which is demodulated by the demodulator 3 and fed to the decoder 4, where the information part of the codogram is extracted and decrypted. At the output of the decoder 4, a signal appears that corresponds to the optimal packet length for the given transmission conditions.

In the signal analyzer 5, for each state of the queue structure in block 7, the order of transmission of packets B is determined for a given optimal: packet length. The transmission is carried out using an encoder 8, a modulator 9 and a transmitter 10. If the packet length K is optimal for transmission at the moment (i.e., the analyzer 5 receives a signal B,), and such a packet

is present (i.e., a signal A is received, ...), then a given packet of duration K;,. If there is no packet length K J, then the packet is transmitted.

length K,., and

etc. (with K, K. K). The imaging unit 6 carries out the work of reading information. Information on block 1 is fed through the elements NOT 20-20, the first elements AND 12-12 through the elements OR 14-14 and

first valves

18, 18 "transmit the signal to the buffer registers 16, - 16,

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15

Claims (1)

Invention Formula 20 A discrete information system with intermediate accumulation containing a packet length determination unit, a serially connected memory block, an encoder, a modulator and a transmitter, and a serially connected receiver, demodulator and decoder, the outputs of which are connected to one input of the signal analyzer, the other inputs and the outputs of which are connected respectively to other outputs of the memory unit and to the inputs of the read signal generator, the outputs thirty 35 40 which are connected to the same inputs; memory unit, characterized in that, in order to eliminate information loss, a packet recording control unit is inserted, the outputs of which are connected to other inputs of the memory unit and to one inputs of the packet length determination unit, the other inputs and outputs of which are connected respectively to the outputs of the block memory and with the inputs of a packet writing control unit. Fi & .g Editor I. Segl Nick Compiled by A.Moskevich Tehred I., Popovich Order 3400/56 Circulation 638Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader A.T. sko