SU1327101A1 - Sequence generator of equidistant random numbers - Google Patents

Abstract

The invention relates to computing and, in particular, can be used in the simulation of random numbers and processes. The purpose of the invention is to increase the accuracy of the generator, i.e. obtaining a high uniformity of distribution of the probabilities of the appearance of binary symbols in the sequence being formed along with a high generation rate. This is achieved by forming an intermediate sequence of binary symbols followed by a random selection of elements for the output sequence by introducing into the device a source containing 1 noise, a generator of 2 clock pulses and a D-flip-flop, 3, additionally n elements OR first 4 and second 5 groups, n elements of 6 delays, n ring registers 7, n groups of elements AND 8, element OR 9, gated discriminator 10.1 Il. cl

Description

The invention relates to computing and can be used in statistical modeling.

The purpose of the invention is to improve the accuracy of obtaining a uniform law of probability distribution.

The drawing shows a block diagram of the generator.

The generator contains a source of 1 noise, a generator of 2 clock pulses, 1 -: trigger 3, elements OR 4 and 5, delay elements 6, ring shift registers 7, elements 8 AND, element OR 9, gated discriminator 10,

The generator works as follows.

In the initial state, in each of the four ring six-bit registers 7, uniform binary generating sequences are written, which are selected based on the following conditions.

The number of variants of six-bit binary sequences is 2. Of these, only 20 sequences have the same number jj o i. meet the condition of uniform distribution and can be used dp education intermediate sequence. Of these 20 binary sequences, such are the ones that, by successive cyclic permutations of their members, give the remaining equally binary sequences, i.e. are generators. They have the following form: 111000, 110100, 110010, 101010.

The signal from the noise source I arrives at the input of the discriminator 10, where the analog signal is converted to digital, followed by decryption in such a way that its signal is formed only at one of its outputs, the signal comes to the input of the corresponding element And 8 of one of four groups of six items. When this occurs, the value of the signal is counted from the corresponding bit of the corresponding ring register 7. The read signal through the corresponding element OR 5 of the second group and through the element OR 9 is fed to the D input of the D flip-flop 3. Through the signal coming from the generator 2 clock pulses per synchronization input of D-flip-flop 3, it takes soy-; This corresponds to the input signal at the D-input, and the signal from the output of the discriminator 10. enters through the corresponding element 4 OR of the first group and the corresponding element 6 of the delay on the shift input of the corresponding register 7, from which the binary number is read. When this occurs, the nt cyclic shift of the generating uniform binary

5 of the sequence recorded in this register. The delay element 6 is required to maintain a constant information in the ring register 7 until the D-flip-flop 3 issues a corresponding bit value of the output sequence. The 2 clock pulse generator synchronizes the operation of the entire device: it gives permission to the discriminator 10 to convert the next value of the analog random voltage value from the source 1 of the shum, and also controls the operation of the P-trigger

0

Formula of Invention

The generator of a sequence of uniformly distributed random numbers, containing a noise source, a clock pulse generator, a D-flip-flop, the output of which is the generator output, characterized in that, in order to improve accuracy, it contains two groups of OR elements, a group of delay elements, a group ring shift registers, p (n is the number of ring shift registers in a group) of groups of elements AND,

5 element OR, gated discriminator, gating the input of which is combined with the synchronization input - D-flip-flop and connected to the output of the clock generator, triggered

the noise source is connected to the information input of the gated decoder, each 1- (i-1, p) group of outputs of which is connected to the first inputs of the elements of the i-th group respectively and to the inputs of the 1st element of the ShZh of the first group, respectively, whose outputs through group delay elements connected to inputs

313271014

The shift of the corresponding ring inputs of the i-gb element OR the second group shift registers, the outputs are different. the groups, respectively, the outputs of the elements of each i-ro ring registers OR of the second group are connected to the shift ram, connected to the second inputs, to the inputs of the OR element, respectively, to the corresponding elements AND the i-th output of which is connected to the D input of the group, the outputs of which are connected to the D-flip-flop.

Compiled by A. Karasov Editor L. Veselovska Tekhred L. Serdyukova Proofreader I. Muska

Order 3390/45 Circulation 672 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk iab., d. 4/5

Production and printing company, Uzhgorod, st. Project, 4

Claims (1)

Claim A generator of a sequence of uniformly distributed random chi ₃₅ villages, containing {source’s noise, clock, D-trigger, the output of which is the generator’s output, characterized in that, in order to increase the exact _{4 0} ty, it contains two groups of OR elements, a group of elements delays, a group of circular shift registers, η (η is the number of circular shift registers in a group) of AND elements, an OR element, a gated discriminator whose gate input is combined with the synchronizing input of the D-trigger and connected to the output clock pulse generator, the noise source output is connected to the information input of a gated decoder, each i-th (ί-1, p) group of outputs of which is connected to the first inputs of the elements of the i-th group, respectively, and the inputs of the i-ro element of the first group, respectively the outputs of which through the corresponding delay elements of the group are connected to the inputs “Shift” of the corresponding ring shift registers of the group, the outputs of the bits of each i-ro ring shift register are connected to the second inputs of the corresponding elements AND of the i-th group, the outputs of which are connected to the inputs of the i-ro element OR the second - groups, respectively, the outputs of the elements OR of the second group are connected to 5 inputs of the element OR, respectively, the output of which is connected to the D-input of the D-trigger.