SU1325489A1 - Information input/output device - Google Patents

Abstract

The invention relates to computing and can be used to exchange data between peripheral devices and computers, as well as to connect computers to a network when creating high-speed control systems. The aim of the invention is to improve the speed. A group of elements OR 8, a command generator 4, a control block 5 (L

Description

Research institutes with the array length and the OR element 9. One or several users, independently of each other at different levels of priority, can start exchange operations, indicating in their assignment a group of subscribers (sources and receivers) and the length of the array (number of elementary exchanges). Into one

ten

15

20

The invention is intended for use in digital computing, in particular for the rapid exchange of data between peripheral devices and computers, as well as for the connection of computers to a network when creating high-speed control systems.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a functional diagram of the device; in fig. 2 - block diagram of the reception and address retrieval; in fig. 3 - block diagram of the receiving and issuing data; FIG. 4 is a priority block diagram; in fig. 5 is a diagram of a command generator; in fig. 6 is a block diagram of controlling the length of the array; figure 7 - diagram of the synchronization unit; Fig. 8 is a diagram of an interface unit with a subscriber; in fig. 9 is a logical node diagram.

The device contains (Fig. 1) block

1 reception and address retrieval (BPVA), block

2 receiving and sending data (BPVD) unit

3 priority (BP), generator 4 commands 25 (GC), block 5 controls the length of the array (BUDDM), block 6 synchronization (BSI), blocks 7 interface with the subscriber (BSA.. VSA, where is the number of subscribers), group of elements OR 8, element 30 ШШ 9, inputs and outputs 10 - 22 devices.

BPVA 1 (Fig. 2) contains the register 23, the elements OR 24, the decoder 25, inputs and outputs 26-30. BPVA is designed to receive addresses from the computer and process them.

BPVD 2 (Fig. 3) contains a decoder 31, the first and second registers 32 and 33, the inputs 34 and the outputs 35. The BBVD is designed for. sharing data

35

The device performs the elementary operation of only one task at a time, however, the processes of all tasks proceed simultaneously and can be interrupted after each elementary exchange operation in accordance with the priority of the task and the readiness of its subscribers. 5 hp f-ly, 9 ill.

0

five

0

50

35

Computer (control panel, etc.) and device units.

BP 3 (FIG. 4) contains a group of elements HE 36, a group of elements AND 37, an element OR 38, a node of elements HE 39, inputs 40, outputs 41 and 42. The BP is intended to suppress the readiness of lower priorities.

GK 4 (Fig. 5) contains the decoder 54, the register 44, the first and second groups of elements And 45 and 46, respectively, the first and second groups of elements SH 47 and 48, respectively. GC is designed to provide an intensive flow of commands to the device blocks in the Autonomous mode in accordance with the current priority.

BUDM 5 (FIG. 6) contains counters 49, a decoder 50, the first and second groups of elements AND 51 and 52, the element OR 53, the one-shot 54, the outputs 55 - 56.

BSI 6 (Fig. 7) contains the scheme OR 57, one-shot 58.

BSA 7 (Fig. 8) contains duplex register 59, decoder 60, logical node 61, trigger 62, one-shot 63, two elements 64 and 65, outputs 66 and 67. BSA is designed to exchange information with the subscriber of the device. The decoder 60 decrypts the binary code of the command.

The decoder 60 recognizes the following types of commands: RD - read, WR - write, RS, SS - selective settings to zero and one, VP - runner, OST - stop, RSD - general reset. Logic node 61 is a combinational circuit realizing a system of equations

VD (Nl WR) v (RD l TSAL P);

20

25

PR (N ARD) v (WRATCAA P),

where N is the individual call signal; Р - entrance of the prergegani; TCA - trigger state 62.5

The trigger 62 is designed to control the logic node 61.

Logic node 61 (FIG. 9) contains five elements AND 68 - 72j elements OR 73 and 74.,.

The device works as follows.

The input-output device has two modes of operation: Center and Anton.

In the Center mode, the computer performs programming of the device equipment, thereby setting up the exchange channels at the respective priority levels. After setting up the computer, the device switches to the autonomy mode, thus starting the exchange channels. Upon termination of each channel in the computer, an interruption occurs due to a corresponding reason. As a result of analyzing these interruptions, the computer removes the fact of the completion of the full task and returns the device to the Center mode for preparing and starting the next task.

To transfer the device to the Center mode, the computer supplies to the corresponding input bit 12 control words at the address of the BPVA 1 logical 1, which enters the BP 3 and, through the element group 35, HE 36 blocks the hardware exchange. In this mode, the computer can perform the operations provided by the system of device commands addressed to any of the program-controlled registers. For example, to record the length of the array in one of the counters 49, the BCDM 5 computer must perform the following actions. At the information inputs 10 to the TDMA 2, the code of the required length of the array is entered. Then, the corresponding bits of the inputs 12 are allocated. operation code Write (in the F field), sub- address of the counter in BUDM 5 (in the A field), physical address BUDM 5 in the interface 50

(in the field M).

I- Based on the synchronization signal at input 11 from the computer BSI 6, it outputs a sync pulse at output 26, which is used to write to the register 23 of the BSVA 1. The physical address of the BCDM is decoded in the decoder 25 of the BPVA 1 and by the outputs of an individual call 29 pos0

five

ABOUT

50

stupidly inputs BUDDM 5. Simultaneously from the outputs of the elements OR 24 BPVA 1, the field of the operation code and the subaddress is fed to the inputs of the BUDM 5 and BPVD 2, TAP 2 perceives the field F and, after decoding the code, output the signal of logical 1 at the output of its decoder 31, opening register 39 and allowing passage of the array length code to information outputs 35 and further to information inputs 51 BUDA 5. BDDM 5 decoder 50, upon receiving an individual call signal at input 29, decrypts the F and A address fields and as a result produces a logical 1 for corresponding vuyuschem depshfratora outlet 30 which strobi- ruets sync with the falling edge of input sync 26 Budmen 5 to provide a delay sufficient to compensate for information transfer delay. By this signal, the information from the information inputs 51 of the BDMM 5 is stored in the corresponding counter 49 of the BCDM 5.

When reading information from the registers of the device blocks, the sequence of action of the computer is as follows. The information inputs 12 of the device are supplied with a MAP command, with the read operation code encoded in the F field. Upon arrival of the clock signal from the computer to input 11, the corresponding outputs 29 and 30 of the ACBU 1 are given an individual call, subaddress A and function F. The addressed unit decrypts the field F, A and outputs the signal of logical 1 at the corresponding output of its decoder, thereby opening the required register. From the register output, the information enters the information outputs of the block. The BPDD 2 decrypts the function and generates a signal of logical 1 at the output of the decoder 31. Just as in the previous case, this signal is gated by synchronization pulses from the inputs 26. By this signal, the information is written to the register 33 of the BPVD 2 and fed to the computer via outputs 16 .

Consider the programming of exchange channels in the I / O device interface.

Suppose two parallel exchanges are required at priority levels P1 and P2. At the P1 level, it is required to send an array of D1 length from

subscriber source with address M

1l

13254896

in the operation Read and vice versa.

nent with a receiver with the address M ,,,, at the level of P2, the exchange parameters have c6 - responsibly the values of the DC, M, en One of the exchange subscribers at each priority should be fixed. Let, for example, at the P1 level the source be stationary, and at P2 the receiver. Then the computer must install in 1 flip-flops 62 stationary subscribers in blocks BSA 7 with addresses In the first of the registers

fO

M, „and M

44 GK 4 operations

gp notes Za15

20

25

There is a command with the code of the letter and the address M, and in the second of the registers 44 of the Civil Code 4 there is a command with the operation code Read and the address. S The first and second of the BUDM counters 49 are recorded in the corresponding lengths of the arrays D1 and D2.

At this programming channel exchange is completed. Then the computer can launch an input operation - - output to the corresponding subscribers. The launch of exchange channels is carried out by switching the device to the Autonomous mode. For this, the computer supplies to the corresponding bit of the inputs of the device 12 at the address of the BSBA 1 a logic signal; who is about to unlock, thus, the outputs of the 41 resolution of interruptions in BP 3. Elementary information exchange operations at this priority level are carried out in the presence of joint readiness and exchange of subscribers of this 35 group and in the absence of those at higher priority levels. At each time point in a single state there may be not more than one of the outlets 41 of the attempts to rip off. provided by the power supply unit 3. If there is a logical 1 at the outputs 41 for shutting down the power supply unit 3, an exchange is performed at this priority level. As a result, the ledger opens the elements of AND groups 64 and 65, allowing the command that is stored; in register 44 of the Civil Code 4, to address 28 and to control 27 outputs. The information from the address bout when performing the next elementary operation corresponding to the given priority level of the exchange, the BUDM 5 counters 49 perform the decrement (subtraction 1). Upon completion of the elementary exchange operation, the subscribers, participating in this exchange, release the corresponding output 40 of the BSA 7 interrupt request. If the current elementary exchange was the last at a given priority level, then the output of the corresponding counter 49 BUDM 5 gives a logical 1 signal, which is fed through the OR 53 element to the output 16 of an individual request and through the single vibrator 54 from the output 56 to the input of the OR 9 element. In this case, an interrupt pulse from the output of the element OR 9 enters the computer at output 17 and an interrupt is triggered in it. The computer localizes the source that caused the interruption of individual requests along the vector. The exchange can also be terminated at the initiative of the subscriber by supplying logical 1 to input 13 of the end of the operation of the corresponding BSA 7.

Claims (6)

1. An information input / output device comprising a data receiving and output unit, an address receiving and output unit, a synchronization unit, a priority unit, the first groups of information inputs and outputs of the receiving and issuing data block are respectively the first groups of information inputs and outputs of the device, the information inputs of the reception and address address block are the device's address inputs, the output and the first input of the device synchronization block, the inputs of the priority block interrupt requests are the inputs of the device 5 interrupt requests Arrangements, characterized in that, in order to improve the speed of the device, a group of elements OR, a command generator, a control unit 28 in the decoder 25 VPVA 1 of the array length, the element OR, is entered into an individual call 29 to a non-stationary (addressable) to the subscriber. The AF address field is perceived at the same time by all subscribers, but only the address —afi and fixed stations of a given priority level react to it. Stationary subscriber during operation Record e Read operation and vice versa. When performing the next elementary operation corresponding to a given level of exchange priority, the BUDM 5 counters 49 perform the decrement (subtraction 1). Upon completion of the elementary exchange operation, the subscribers, participating in this exchange, release the corresponding output 40 of the BSA 7 interrupt request. If the current elementary exchange was the last at a given priority level, then the output of the corresponding counter 49 BUDM 5 gives a logical 1 signal, which is fed through the OR 53 element to the output 16 of an individual request and through the single vibrator 54 from the output 56 to the input of the OR 9 element. In this case, an interrupt pulse from the output of the element OR 9 enters the computer at output 17 and an interrupt is triggered in it. The computer localizes the source that caused the interruption of individual requests along the vector. The exchange can also be terminated at the initiative of the subscriber by supplying logical 1 to input 13 of the end of the operation of the corresponding BSA 7. Invention Formula 1. An information input / output device comprising a data receiving and output unit, an address receiving and output unit, a synchronization unit, a priority unit, the first groups of information inputs and outputs of the receiving and issuing data block are respectively the first groups of information inputs and outputs of the device, the information inputs of the reception and address address block are the device's address inputs, the output and the first input of the device synchronization block, the inputs of the priority block interrupt requests are the inputs of the device interrupt requests Properties, characterized in that, in order to increase the speed of the device, a group of OR elements, a command generator, an array length control unit, an OR element, and The group of informational outputs of the receiving and data block is connected to the first group of inputs of the elements OR groups, the outputs of which are connected to the second group of information inputs of the receiving and outputting data block, information inputs of the command generator and the array length control unit and are the second group of information outputs of the device, the control input of the priority block is one of the address inputs of the device, the resolution outputs of the priority block interrupt are connected to the resolution enable inputs of the array length control unit, command generator, and the output outputs of the device interrupt control output the priority block is connected to the second input of the synchronization block, the output of which is connected to the synchronization inputs of the receiving and issuing block of data, the receiving block and the address of the generator commands, an array length control block, the output of the service request block of the array length control is connected to the input of the OR element, the output of which is the output of the device service request, the input group of the OR element is the inputs of the device service request, the information outputs of the array length control block are connected to the second group the inputs of the elements of the OR group, the third group of inputs of which is the second group of information inputs of the device, the output of the individual request of the control unit of the array length Is the information output of the device, the information outputs of the receiving and address block are connected to the address ones. the inputs of the data receiving and output unit, the command generator and the control unit. the array length and are the third group of information outputs of the device; the outputs of the individual call of the receiving unit and issuing the address are connected to the inputs of the individual call of the array length control unit, the command generator, and are the outputs of the individual call of the device the address and control outputs of the general The commands are connected to the corresponding address and control inputs of the receiving and receiving unit. 2. The device according to claim 1, characterized in that the command generator comprises a decoder, registers, two groups of elements AND, two groups of elements SH, information inputs of the decoder are address inputs of the generator, the synchronizer input of the decoder is connected to the first inputs of elements AND of the group and is the synchronization input of the generator, the control input of the decoder is the input 5 o 5 o g 0 uh five individual generator call, the outputs of the decoder are connected to the corresponding gate inputs of the registers, the information inputs of which are information inputs of the generator, the second inputs of elements AND groups are inputs of enabling the generator interrupt, the first and second groups of outputs of registers are connected to the group of inputs of elements And the first and second groups respectively, the outputs of the elements of the first and second groups are connected to the inputs of the elements OR of the first and second groups, respectively, the outputs of the elements OR of the first and second The second groups are address and control outputs of the generator, respectively, 3. Device POP. 1, characterized in that the array length control unit contains counters, a decoder, two groups of AND elements, an OR element, a one-shot, the decoder's information inputs are the address inputs of the block, the decoder synchronization input is connected to the first And inputs of the first elements the group and is the synchronization input of the block, the control input of the decoder is the input of the individual call of the block, the second inputs of the And elements of the first group are the enable inputs of the block interrupt, the inputs of the initial installation of the counter Cove are information input unit, and outputs elements of the first group are connected to the inputs of the decremental counter, the group decoder outputs is connected with the corresponding synchronization inputs of the counters, the output of the decoder is connected to the first inputs of the elements of the second group, the outputs of the counters are connected to the second inputs of the elements of the second group and the inputs of the SH, whose output is connected to the input of the single vibrator and the output of the individual block request, the output of the single vibrator is the output of the request for service block, the outputs of the elements And the second group are the information outputs of the block. 4. The device according to claim 1, characterized in that the priority block contains a group of elements NOT, a group of elements AND, an element OR, whose output is the control output of the block, the inputs of the elements NOT of the group are the control input of the block, the outputs of the elements NOT the groups are connected to the first inputs of the elements — AND groups, the second inputs of which are the inputs of the interrupt request of the block, the outputs of the elements AND groups are connected to the inputs of the OR element, the inputs of the node of the elements are NOT and are the outputs of block interruption resolution, the outputs of the node elements are NOT connected to the corresponding decoder, register, informational inputs of elements AND groups. the inputs of which are the information 1-block inputs, the control input of the register is the synchronization input of the block, the register OUTPUTS are connected to the first group of inputs of the IL elements the second and third groups of inputs of the OR elements are respectively the address and control inputs of the block of the outputs of the OR elements are connected to the inputs of the decoder and are the address outputs of the block, the outputs of the decoder are outputs of the individual call block. 5. The device according to claim 1, wherein the receiving and transmitting unit contains a decoder, two registers, the information inputs of the decoder are the address inputs of the block, the information inputs of the registers are respectively the first and second groups of information inputs of the block, information outputs of the registers respectively the second and first groups of information  21 the block outputs, the control input of the decoder is the synchronization input of the block, the outputs of the decoder are connected to the control inputs of the registers. I 6. The device according to claim 1, characterized in that the receiving and receiving unit contains the elements OR, descrambler, register, informational the inputs of which are information 1-block inputs, the control input of the register is the synchronization input of the block, the register OUTPUTS are connected to the first group of inputs of the elements OR the second and third groups of inputs of the elements OR are respectively the address and control inputs of the block, the outputs of the elements OR are connected With the inputs of the decoder and the address outputs of the block, the outputs of the decoder are the outputs of the individual call of the block. TO 24 :} 29 2 30 26 I Record THAT 32  35 sixteen  Figz FIG. 7 Editor L. Gratilllo Compiled by I. Karpova Tehred L. Serdyukova Proofreader M. Pojo Order 3111/45 Draw 672 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 9