SU1316037A1 - Device for recording digital information - Google Patents

Abstract

The invention relates to the field of information accumulation. The purpose of the invention is to increase recording density while maintaining clock and block synchronization by increasing the information content of the recording signal. The device contains a shift register 1, a pulse counter 3, a frequency divider 4, a pulse distributor 6, a pulse counter 7, a decoder 8, a register 9, a counting trigger 10, a recording amplifier 11, elements 12-16, elements OR 17 and 18, and element 19 delays. The introduction of new elements and the formation of new connections between the elements of the device allow the formation of a three-frequency recording signal, in which every eighth cycle switches the signal from one level to another, which provides both clock and group synchronization, 1 sludge. (L 00 05 about with

Description

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The invention relates to the field of accumulation of information, namely to 1WLR information recording devices.

The aim of the invention is to increase the recording density while maintaining clock and block synchronization by increasing the information content of the recording signal.

The drawing shows a functional diagram of the device.

The device for recording digital information contains shifts of the shy register 1 connected by the information input to the information bus 2, the first synchronizing input to the output of the first counter of 3 pulses connected by the input to the second synchronizing input of the shift register 1 and the output of the D frequency connected to the input sync bus 5 and to the input of the distributor 6 pulses. The pulse distributor 6 is connected by one output to the setup input of the second pulse counter 7, connected by outputs to the inputs of the decoder 8 and the input to the first output of the shift register 1 connected by the second output to the input of the static register 9. The device also has a series-connected counting trigger 10 and an amplifier 11 entries. In addition, the device for recording digital information contains the first - fifth elements AND 12-16, the first and second elements OR 17 and 18, and the delay element 19 connected between the first synchronization input of the shift register 1 and the output of the first pulse counter 3, connected by an output to the interconnected installation input of the distributor 6 immersion and the first input of the first element OR 17. The latter is connected by the second input to one of the outputs of the decoder 8 and the output to the first input of the first element 12 connected to the second input the second output of the distributor 6 pulses and the output to the input of the counting trigger 10. The second, third, fourth and fifth elements And 13, 14, 15 and 16 are connected by the first inputs to the corresponding outputs of the decoder 8 and the outputs to the remaining inputs of the first element OR 17, static register 9 is connected by the first output to the second input of the fourth

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And 13, the second input to the interconnected second input of the fifth element And 16 and the input of the second element OR 18, connected by output to the second input of the third element AND 1D and the inverse input connected to the interconnected third output of the static register 9, the inverse input p of the element E 16 and the second input of the second element I 13.

The proposed device for recording digital information provides the formation of a three-frequency signal

15 records with information capacity of 1, 5 bits for a minimum period with the possibility of performing both clock and group self-synchronization of the playback signal.

0 Functionally, the recording signal is formed by dividing the initial information into groups containing a certain number of bits of the recorded information, then it performs 5 with the transcoding of information and the formation of a recording signal using the KVNM method. In the scheme under consideration, the recorded information is divided into six-bit groups, of which

0, eight-bit codes are formed that do not contain more than two zeros of the sequence. Sync pulses arriving at the syncronized bus 3 pass to the inputs of the distributor 6 pulses and the healer 4 pulse frequency, ensuring its division into four. The pulses from the output of the divider 4 pulse frequency are fed to the input of the counter 3 pulses jpeQ of the read information. The latter ensures the formation of a pulse on every sixth cycle, corresponding to the passage and recording on register 1 of a six-bit group of information. The pulse from the output of the counter 3 pulses of the recorded information phases the operation of the distributor 6 pulses and after a delay on the delay element 18 enters the input

n register 1.

The signals from the outputs of register 1 (in the considered variant) are divided into two three-digit groups. The first trirazr bottom group arrives

, to the installation inputs of the bits of the second counter 7 pulses. The signals from the outputs of its bits are fed to the inputs of the decoder 8. To the input of the second counter 7 pulses are received im5

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iiyjihci i with vr.1khg) and the third phase of the distributor 6 img pulses. A distinctive feature of the second counter 7 pulses is that it carries out at its overflow the hydraulic transfer of the overflow signal to the low order, i.e. the zero state of the pulse counter 7 is eliminated, although zero states can be written to the installation inputs in all three bits.

In accordance with the state of the pulse counter 7, signals are sequentially generated at the outputs of the decoder 8. In this case, code 100 corresponds to the signal at the first output, state 010 at the second, and so on. No signals are generated only for code states 000 and 011.

The code value of the information is recorded on a static register 9, from the outputs of which the screens are fed to the corresponding inputs of the AND 13–16 logic elements and the OR 18 element. The inputs of the And 13–16 elements receive signals from the corresponding decoder 8 outputs. at the output of the OR element 17, a time signal is formed corresponding to the code for converting the six-bit code of the source information into an eight-bit code not matching more than two zeros of the order. As a result, the signals from the output of the second phase of the distributor 6 pulses ostupayuoshm the input element of the AND 12 is formed at its output a pulse signal to Eight-stand sequential code.

The signal from the output of the And 12 element is fed to the input of the counting trigger 10, as a result of which an information recording signal is generated at its output. After the necessary amplification at the recording amplifier 11, the signal is fed to the output of the device and then fed to the magnetic head of the recording device (not shown).

Thus, the considered device provides the formation of a three-frequency recording signal, in which every eighth clock cycle in a mandatory order switches the signal from one level to another, which provides both clock and group synchronization. The recording capacity of the recording signal is 1.5 bits for a minimum period. The ratio of the intervals between

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the neighboring switchings of the N. chaudie in the ratio 1: 2: 3.

Claims (1)

Isorrhen formula A device for recording digital information containing a shift register connected by an information input to an information bus, a first synchronization input to the output of a first pulse counter connected by an input to interconnected second synchronizing input of a shift register and an output of a frequency divider connected to the input of a synchronizing bus and to the input pulse distributor connected by one output to the setup input of the second pulse counter connected by outputs to the decrypted inputs a and an input with the first output of the shift register connected by the second output to the input of the static register and serially connected counting trigger and recording amplifier, characterized in that, in order to increase the recording density while maintaining the clock and block synchronization by increasing the information content of the recording signal, It contains the first, second, third, fourth, and fifth elements of AND, the first and second elements of OR, and a delay element connected between the first synchronizing input of the shift register and the output of the first pulse counter connected by the output to the NFy input of the pulse distributor connected to each other and the first input of the first OR element connected by the second input to one of the decoder outputs and the output of the first input I connected to the second input of the pulse distributor and output to the input of the counting trigger, the second, third, fourth, and fifth elements of AND are connected by the first inputs to the corresponding outputs of the decoder and outputs to the remaining inputs of the first element OR, while the static register is connected by the first output to the second input of the fourth element AND, the second input to the second input of the fifth element AND interconnected and the input of the second OR element connected by the output to the second input of the third 513180376 of the element I and the inverse input of the sub-nest, the inverse input of the fifth elecruise to the connected one between the item I and the second input of the second eleboy the third output of the static repeater I.