SU1315968A1 - Device for sorting numbers - Google Patents

Abstract

The invention relates to automation and computing and can be used in the implementation of data processing systems and automated control systems. The device contains registers, comparison schemes, groups of elements AND, result register, counter, adder, two blocks of elements AND, a group of prohibition schemes. New in the device is the use of upper and lower boundaries of the range, groups of AND elements, IL elements, two registers, an additional comparison circuit, the NAND element, three delay elements, an array size counter, three AND elements, a block of AND elements, a trigger and their connections, which ensures the achievement of the objectives of the invention. The aim of the invention is to expand the scope by ordering numbers in a given range. Sorting numbers can be performed both within the entire source array, and in a given range. The sort mode is set by varying the numbers in the lower and upper range registers. The operation of the device consists of two stages. At the first stage, the bounding array to be ordered is determined by alternately comparing the given lower bound with each of the numbers in the original array. At the second stage, the polling pulses generate a memory address for placing the analyzed number from the signals from the comparison circuits of the Less and Equal groups. When retrieving from the device, the number is compared with the upper limit. If it exceeds the set value, then simultaneously with the address a zero number is output for the record. The operation of the device is completed upon completion of viewing all the numbers of the array, limited in the first stage. 1 ill., 1 tab. i 00 01 CD O 00

Description

The invention relates to automation and computing and can be used in the implementation of data processing systems and automated control systems.

The purpose of the invention is the expansion of the field of application due to the possibility of sorting numbers in a given range.

The drawing shows a block diagram of the proposed device.

The device contains a register 1, a comparison circuit 2, a group of IZ elements, a result register 4, a counter 5, an adder 6, a group of elements I 7, a group of elements I 8, a group of elements I 9, a register to, n elements of ILR 11, a register 12, AND-NE 13 element, AND 14 group of elements, prohibition element group 15, AND 16 output element group, AND 17 group of output elements, AND elements 18 and 19, delay elements 20 and 21, upper limit register 22, additional comparison circuit 23 , delay element 24, register .25 lower bound of the range, group of elements And 26, element And 27, trig ger 28, array size counter 29, device range upper limit inputs 30, device range lower limit outputs 31, device start input 32, device start address inputs 33, device polling input 34, output devices 35. sorted device number, number address outputs 36 devices, outputs 37 of the size of the device array, output 38. read resolution of the device.

Consider the principle of construction and operation of the device.

The initial state of the device is characterized by the fact that the trigger 28, the registers 10 and 12 and the counter 29 are set to the state O (not shown).

The device can be used in two number sorting modes. B the first of them. the numbers are sorted within the entire source array, received in registers 1, and in the second, in a given range. The sorting mode is set according to the contents of the lower limit register register 25 and the upper limit register register 22. In this case, to set the first mode, all bits of the register 25 are set to

O, and registers 22 are in state 1, thereby overlapping the entire range of sorted numbers.

For setting the second mode of sorting numbers, the binary code of the lower limit of the range is accepted into the register 25, and the binary code of the upper limit of the range of the binary is entered into the register 22. Varying the values of the boundaries of the range, you can set or sort the numbers smaller than the pre-set by setting the state of register 25 to O, and in register 22 the binary code of the upper limit, either by sorting numbers larger than the set-preset, by setting the border in register 25, and the bits of register 22 are in state 1. Let it be necessary to sort the numbers in a given range, To do this, register 1 holds an array of source numbers, in register 25 the limit of the lower tolerance (number), and in register 22 the border of the upper numbers

range (agr) The operation of the device is divided into two stages. The first stage starts at the trigger signal inputted at input 32. Since trigger 28 is set to state O, the I 26 border elements are opened with a single signal from its zero output. In this case, the second inputs of all comparison circuits 2 are supplied with a binary register code 25. The first inputs of the comparison circuit receive a binary code from the corresponding register 1, Scheme 2. comparison, on the first inputs of which the code of the array number is greater than the specified one.

0

five

, they form at the outputs more single signals arriving at the first inputs of the corresponding elements of AND 9. When a start signal is present, the state 1 of the same name of the registers 10 and 12 is set through the open corresponding elements of AND 9. Thus, using the register 10 later participation in sorting numbers is allowed,

„Large values a ,, g i 0

Register 12 is intended for sequential analysis of the contents of register 1, whose numbers unambiguously correspond to the numbers of register bits 12 set to state 1.

After some time delay determined by transients in the AND elements 9, through the delay element 24 the trigger 28 is set

3,

In addition, the zero signal from the zero output of the trigger 28 blocks the supply of a binary code and HV to the comparison circuit 2, thus eliminating its effect on the further operation of the device. This completes the first stage of operation of the device.

The second stage of the device begins with the presence of a zero signal at output 39, which enables the injection of polling pulses at input 34. At this stage, the address of the memory cell and the code of the number to be recorded are formed for each polling pulse in the device.

The cell address is formed in adder 6 by the following expression:

A ,. (, 2,. ,,, s),

where A. is the memory address in the i-th cycle

device operation, N. is the number of numbers less than the analyzed number in the i-th cycle, K. is the number of numbers equal to

the analyzed number in the i-th cycle

S - the number of numbers large

At that, the value of AH is fed to adder 6 through inputs 33, and the sumN; + + K. formed by counter 5.

159684

The number of polling pulses is determined by the number of large numbers. as evidenced by the number of bits of registers 10 and 12 set to 5 in state 1 in the first stage. At the end of each polling cycle, the corresponding register bit 12 is set in О and the contents of counter 29 are increased by one unit with more nonzero information at outputs 35.

The end of the operation of the device is determined by the zero state of the register 12. In this case, the counter 29,

ten

15

20

25

thirty

the number of sorted numbers is fixed, and the trigger 28 is set to the state O. A single signal from the zero output of the trigger, which arrives at the output 39 of the device, is used as a signal to end the sorting of the array of numbers.

Consider the operation of the device with the following numbers and received in registers 1:

,,,,

Let it be necessary to obtain an ordered array of numbers as, a.9, placing it in the memory area, starting with an address.

Under these conditions, the device's operation is shown in the table, in which the arrows indicate the voltage to write numbers from registers 1 to the memory.

1 2 3 4 .5 6 7 8

9

7 3 3 2 1 3 4

2 3 3 3 4 7 О

51

After the device has been reset to registers 1, 22 and 25, the binary codes of the respective numbers are applied.

Since the trigger 28 is in the zero state, the single signal from its zero output opens And 26 elements, and the number is compared in circuits 2, ..., 2d compared to the contents of the corresponding registers 1. At the same time, the outputs , except for 2, single signals are generated that arrive at the first INPUTS of elements AND 9. At the first input of element AND 9, there is a zero signal from the output of the More circuit 2 of the comparison.

The trigger pulse through open elements AND 9 is set to 1 the corresponding bits of registers 10 and 12. Elements 11 11 provide a paraphase method of setting 1 bits to register 12 for faster switching of the trigger state. Thus, at the outputs of registers 10 and 12, the following code is set: 1.1111011.

Simultaneously with the installation of registers 10 and 12 in 1 trigger by a delayed start signal element

A 24 delay is set to 1 trigger 28, thereby blocking the effect of the register output signals

25 through the elements of AND 26 for all circuits 2 comparisons.

Zero signal from zero zero trigger 12 closes the elements 15, ..., 15, prohibition, the outputs of which are set to zero signals. Therefore, only elements AND 3 are opened with a single signal from a single trigger output 12.,. The binary code of the number 9 from register 1j is transmitted to register 4 and to the second inputs of circuit 22, ..., 2g comparisons, which form single signals at the Menshe outputs. Since the second inputs of the comparison circuit 2 are zero, the output is More - single. Thus, at the first inputs of the And 7 elements, a code 01111111 is generated by the output signals from the outputs Smaller

schemes 2, ..., 2g, and

on

the second is code 11111011 from the outputs of register 10. At the same time, the value of N. is 6. Since there are no signals at the outputs of Equal to all 2 comparison circuits, the value of K-) 0. Therefore, the amount of 5968

five

0

five

0

five

0

five

0

the torus forms the address of the memory cell

A 1 + 6 + 0 7.

After completion of the transient processes in the adder 6, the zero signal from the output 39 of the device to the computer is allowed to feed the polling pulses to the input 34 of the device.

Since the inputs of the element And 13 are supplied with signals from the zero outputs of the register 12, a single signal is formed at its output, the opening element And 18 through the third input. The single signal from the single output of the trigger 28 opens the first inputs of elements 18 and 19. Since register 4 contains the code of the number 9, and register 22 has the same code, the output of the Less comparison circuit 23 produces the zero signal, the closing element AND 18.

Therefore, the first polling pulse comes only through the open element AND 19. This signal through the element 16 and the outputs 36 transmits the binary code of address A., followed by control of the signal from output 38. By the signal from the output 3S of the device, the address information from the outputs 36 and numerical information from outputs 35 is received for writing to the memory. Since AND 18 is closed, zero information will be written to the address in the memory.

After some time delay determined by the time for reliable reception of information from outputs 36 and 35 in the computer, by a polling signal - through delay element 20, the open element is AND 14., and the OR 11 element is set to O by trigger 12. In this case, with a single signal from its zero output, the elements E15 are opened, and 15 through the corresponding inputs, and with a zero signal from the zero output of the trigger 122, the elements 15 And 15 ,, are closed. . ., And 15. At the outputs of register 12, the following code is set: 01111011.

Since the code 1000000 is formed at the outputs of the AND 15 elements, the single signal from the output of the AND 15 element opens the elements OF, and the code of the number 7 from the outputs of register 1 is compared in all comparison circuits except 2. 5 with the contents of the corresponding registers. In addition, in the adder 6, the address A is formed similarly to that considered.

A2 I-5 + 0 6.

Since the code of number 9 is in register 22- and the code of number 7 is in register 4, a smaller signal is established at the output of the comparison circuit 23, and an element 18 is opened at the second input. Therefore, at the next interrogation pulse arriving at the input 34, through the open elements And 18 and 19 to the outputs 36 through the elements And 16 is transmitted to the computer

the address code is A2, and the outputs 35 through AND 17 elements are the code of 7 from register 4. At the same time, the signal from the output of element AND 19, arriving at the output 38 of the device, similarly to that considered, provides for receiving address and numeric information in the computer.

The output signal of the delay element 20 through the open element And 14 and the element OR 11 is set to O flip-flop 12, the code 00111011 is generated at the output of the register 12 and the output of the elements of the 15 and 15 is the code 0100000. which keeps the AND element 18 in the open socket at the third input, and the closed state - the AND element 27 at the inverse input.

A single signal from the output element And 1 Sj. the elements are open and the rear, and the binary code of the number 3 is compared in comparison circuits, except 2, with ko-. With the respective registers 1. At the same time, at the outputs, Fewer comparison circuits 25 and 2 and at the outputs Equal to comparison circuits 24 and 2, single signals are formed.

Since code 11111011 is present at the second inputs of And 8 elements, And And 7 is closed, so Nj 1

 Since code 00111011 is present at the second inputs of the And 8 element, the And 84. and 8-j elements are open, therefore.,.

On this basis, binary code Aj is formed in adder 6.

AZ 1 + 1 + 2 4.

On the next polling pulse, the code Aj and the code of number 3 are issued in the computer, the trigger 12j is set to O, and the code of number 2 is generated in the counter 29.

In the future, the operation of the device is carried out similarly, as reflected in the table.

Alternately, the installation in O of the triggers of the register 12 successively excludes when generating the value of K the signals from the outputs are Equal to 2 comparison circuits.

Considering that a single signal from the output Less than the 2g comparison circuit from the formation of the address is excluded, the values of the address codes are:

.A4 1 + 1 + 1 3,

Aj 1 + 0 + 0 1.

Since the trigger. 12 on the first

stage remained in the state

that

0

five

0

five

analysis of the contents of register 2 is excluded. Therefore, according to the next survey impulse fop shpkyts A.

  +

and then on the next survey pulse - Ag

Ag 1 + 4 + 0 5.

The seventh polling pulse in the counter 29 generates the code of number 6, all the triggers of register 12 are O. At the same time, at the output of the NAND 13 element, a zero signal is formed, the closing element AND 18 at the third input and the opening element AND 27 at the inverse input . Upon completion of the transition processes in the elements of AND 14 and OR / 11, register 12, element AND-NOT 13, the delayed polling pulse from the output of delay element 21 through opening element 27 is set to O trigger 28. Single signal from zero trigger output 28 is output 39 and is used in a computer as a signal to complete the sorting of an array of numbers. By this signal, the computer can use the value of the binary code of the number of numbers written in the memory from output 37,

To sort the numbers within the entire array, register 25 sets the zero code, and register 22 sets the maximum code value. At the first stage, all triggers of registers 10 and 12 are set to -1 and the numbers are sorted after n polling pulses.

913

Claims (1)

Invention Formula A device for sorting numbers containing n registers, (n is the number of sorted numbers), n comparison circuits, n groups of elements I, a counter, adder, two groups of output elements AND, a result register and a group of (n – 1) prohibition elements the outputs of the bits of the i-ro register (, 2, ..., p) are connected with the first group of inputs of the i-th comparison circuit and with the first inputs of the elements of the i-th group, the outputs of which are connected to the (i-1) -th groups inputs of the comparison circuits with the first through (i-1) th, with the i-th groups of inputs of the comparison circuits with ((i + 1) th through p-th. and with the i-th group of inputs of the result register, the bit moves of which are connected to the first inputs of output elements AND of the first group whose outputs are the outputs of a sorted device number, the outputs of the counter bits are connected to the first group of inputs of the adder, the second group of inputs of which are connected to the inputs of the initial address of the device, and the outputs from the first the inputs of the output elements AND of the second group, the outputs of which are the outputs of the address of the sorted number of the device are the 1st inverse inputs of the elements of the prohibition of the group, where, 2 ,,,., j, j 1,2 ,. , .., n-1 are combinable, characterized in that, in order to expand the scope due to the possibility of sorting numbers in a given range, the registers of the upper and lower limits of the range, the group of elements And the rewriting of the lower limit of the range, four Census groups of elements, two n-bit registers, n elements OR, NAND element, an array size counter, three AND elements, three delay elements, a trigger, additional, a comparison circuit, the device start input connected to the first inputs of the AND elements the census of the first group and Erez ki delayed first element to the input of the installation in a single trigger state, inversnvy output of which is the output end of the sorting apparatus and is connected to the lane vym inputs of AND census lower range, the second inputs of which are connected to the outputs of bits lower boundary register diapazo25 596810 The inputs of which are the inputs for setting the lower limit of the range of the device, the outputs of the elements And the census of the lower bound; 5 to the additional groups of inputs of all the comparison schemes, the output of the More i-th comparison scheme is connected to the second input - the i-ro element And the census of the first group, the output of which is connected  О with the installation inputs into the single state of the i-ro bit of the first and second n-bit registers, the direct output of the i-ro bit of the first n-bit of the first register is connected to the first input  5 i-ro element And census of the second group, the second input of which is connected to the output Less than the i-th comparison circuit, output Equal to which is connected to the first input of the i-ro element And census 20 of the third group, the second input of which is connected to the direct output of the i-ro bit of the second n-bit register, the inverse output of the 1st bit of which is connected to the G th inverse input of the j-th group prohibition element and to the input of the I element -NON, the output of which is connected to the first input of the first element AND and the first inverse input of the second element AND, the output of which is connected to the input us-. settings in the On trigger, the direct output of which is connected to the second input of the first element And and the first input of the third element And, the second input 35 which is combined with the third input of the first element And is the input: polling the device, and the output is the output resolution of the device readout and is connected to the second inputs of the output elements AND of the second group and the input of the second delay element whose output is connected to the first inputs of the elements And the census the fourth group and through the third element, the delay is connected with the second input of the second element And the outputs of the elements And the census of the second and third groups are connected respectively with the first and second groups of inputs of the counter, inverse to The output of the i-ro bit of the first n-bit register is connected to the first input of the i-ro element OR, the second input of which is connected to the i-ro output. element And the census of the fourth group, and the output is connected to the input of the installation in the О i-ro bit of the second n-bit register, the direct input j-ro element of the group ban is connected to the right 30 40 45 50 55 my code (j + 1) -ro bit of the second n-bit register, direct output of the first bit of the second n-bit register connected to the second inputs of the AND elements of the first group and the second input. The first element And the census of the fourth group, output The j-ro element of the prohibition group is connected to the second inputs of the elements of the AND (W + 1) -th group and the second input (j + O-ro of the element AND census of the fourth group, the inputs of the upper limit of the device range are connected to the inputs The upper limit of the range, the bit outputs of which are connected to the first group of inputs of an additional comparison circuit, the second group of inputs of which is connected to the outputs of the bits of the result register, and the output is connected to the fourth input of the first element And whose output is connected to the second inputs of output elements I. the first group and the counting input of the array size counter, the bit outputs of which are included in the device array size outputs. Compiled by E.Ivanova Editor S.Pekar Tehred L.Oliynyk Order 2363/50 Circulation 672 Subscription VNIIPI State Committee GCCP for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., d, 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader M. Demchik