SU1309169A1 - Device for protection of current inverter - Google Patents

Abstract

The invention relates to electrical engineering, in particular, to devices for protecting thyristor current inverters from short-circuit conditions. The aim of the invention is to increase the reliability of the device for a sanuiTbi current inverter during start-up. If there are no pulses from the inverter bridge thyristor 3 reverse voltage sensors 3 during start-up (for example, when the inverter starts a short circuit), element 15 does not change its output potential and a single potential continues to be present at the second input of element 11 19 . At the first input of the element AND-HE 14, at a selected start time (less than the period of the inverter output voltage), a unit potential is also supplied and a zero signal is removed from the output of the AND-HE element 14, which blocks the element 12, which is output the pre-zero (zero) signal. Thus, the rise time of the short-circuit current during start-up is always shorter than the period of the inverter output voltage, which significantly limits its amplitude. 2 Il. F (L C anode ruppe / t muflucmo / oe C of the cathode group of thyristors with о с S with Fig. 1

Description

The invention relates to a converter technique, in particular to devices for protecting thyristor current inverters from short-circuit conditions.

The aim of the invention is to improve the reliability of the device to protect the current inverter during start-up.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 - voltage diagrams on the elements of the device (the indices on the voltage diagrams correspond to the numbers of the elements).

The device contains a master oscillator 1, the output of which is connected to the input of the converter unit 2, two identical channels for the anodic and cathodic groups of valves, each of which includes a sensor of 3 reverse voltages connected to the first input of the element AND –NE 4 through a shaper of 5 rectangular pulses , the element OR 6, the inputs of which are intended to be connected to the corresponding outputs of the counting unit 2, and the output is connected to the input of the former 7 narrow rectangular pulses, the output of each former 7 narrow rectangular pulses pulses connected to the second input of the element AND-NOT 4 of this channel and to the counting input of the element MEMORY 8, included in another channel, the output of the element IS-NOT 4 of each channel is connected to the potential input of the element MEMORY 8 included in this channel, the outputs of the SAM elements 8 are connected to the inputs of the AND 9 element, the start block 10, the output connected to the R input of the first RS flip-flop 11 and to the first input of the output element I 12, the direct output of the first RS flip-flop 11 is connected to the R input of the second RS flip-flop 13, the direct output of which is connected to one of the additional inputs of the robust element AND-HE 14, another input of which is connected to the output of the element AND 9, whose inputs are connected to the outputs of the elements of MEMORY 8, the second input of the output element AND 12 is connected to the output of the additional element AND-NOT 14, the S inputs of the first 11 and the second 13 RS-flip-flops are designed to be connected to the corresponding outputs of the scaler 2.

The device works as follows.

At the point in time before the inverter starts, the zero signal from the start block 10, which sets the mode of operation of the inverter (on - off), sets the RS-flip-flops 11 and 13 to a state where zero potential is present at their direct outputs.

At the output of the element And 9 there is a single signal (since there are no signals from the inverter reverse voltage sensors).

From the output of the element AND-NOT 14, a single signal is applied to the input of the element And 12, on the first input of which there is zero 5

potential from block 10 run, resulting in the output element And 12 in the control system of the inverter receives a inhibitory (zero) signal.

When a signal is sent to turn on the inverter at the time ti (Fig. 2) from the start-up unit 10, a unit potential is applied to the R input of the RS flip-flop 11 and the first input of the And 12 element. As a result, with

the output of the element 12 into the control system of the inverter receives a single signal at time ti (Fig. 2).

The RS flip-flop 1 1 is transferred across the S-input of the pulses from the conversion unit 2 to, for example, the 1st pulse at time 12 of FIG. 2) and a single potential appears at the R input of RS flip-flop 13. The time represented for the start of the current inverter with “protection blocked (FIG. 2) (blocking by RS-trigger 13 of the element

0 AND-NO 14) is selected by selecting a pulse from the conversion unit 2, which is fed to the S input of the RS flip-flop 13, for example, when the 5th pulse is applied, the time represented for the start is equal to 240 el. hail., and for the 6th pulse - 300 el. hail, the period of the output voltage of the inverter. As soon as the RS flip-flop 13 on the S-input changes its state to the opposite, the blocking of the AND-NO element 14 on the first input is released. If during this time signals from the inverter bridge valves are received, signals about the normal operation of the inverter, then the zero potential is removed from the output of element And 9, as a result of which the output of element AND-NOT 14 contains a unit potential that goes to the second, and the input of element And 12, at the first input of which there is also a single potential from the starting block 10, therefore, from the output of the element I 12, the permitting signal (single) is fed to the inverter control system.

0 If there are no pulses from the inverter bridge valve's reverse voltage sensors during start-up (for example, when the inverter is started for a short circuit), AND 9 does not change its output potential, and a single potential continues to be present at the second input of the IS 14 element. After the selected start time t4 (less than the inverter output voltage period), the unit potential is also fed to the first input of the element I-14, and a zero signal is removed from the output of the IT-14 element, which blocks the element I 12, which is output to the inverter control system a inhibitory (zero) signal is applied. Thus, the rise time of the short-circuit current during start-up is always less than the period of the inverter output voltage, which significantly limits its amplitude.

0

Claims (1)

Invention Formula A device for protecting a current inverter equipped with a master oscillator connected to a scaling unit, contains an element And two identical channels for the anodic and cathodic groups of valves, each of which includes a reverse voltage sensor connected to the first input of the element AND-NOT through a rectangular driver pulses, an OR element whose inputs are intended to be connected to the corresponding outputs of the counting unit, and the output is connected to the input of a shaper of narrow rectangular pulses, the output of each shaper Narrow rectangular pulses are connected to the second input of the NAND element of this channel and to the counting input of the MEMORY element included in another channel, the output of the NAND elements of each channel is connected to The social input of the MEMORY element included in this channel, the outputs of the MEMORY elements are connected to the inputs of the AND element, characterized in that, in order to increase the reliability at the start, it is equipped with a trigger unit, first and second RS-triggers, an additional AND-NOT element and output element And, the S-inputs of the first and second RS-flip-flops are designed to be connected to the corresponding outputs of the scaling unit, the output of the launcher is connected to the R-input of the first RS-flip-flop and the first input of the output element And, the direct output of the first RS-flip-flop is connected to R-input of the second RS-flip-flop, a direct output of which is connected to the first input of the further AND-NO element, to second input of which is connected an output of AND, yield an additional AND-NO element is connected to the second input of the output member I.