SU1309047A1 - Analog multiplying device - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in devices in which it is required to multiply two analog values, squaring or extracting from the root, as well as division. The aim of the invention is to improve the accuracy of the device. This goal is achieved by introducing a second inverter 5 and a fourth switch 1, which significantly reduces the influence of the main components of the error of modern integrated signal multipliers and makes it possible to use integrated multipliers without external adjustments. 2 Il.

Description

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4 The invention relates to the field of automation and computer technology and can be used in devices in which it is required to multiply two analog values, squaring or extraction from the root, as well as division. The aim of the invention is to improve the accuracy of the device. FIG. 1 shows a functional diagram of the device; in fig. 2 is a timing diagram of the switch control signals. The device contains a switch 1-4, the multiplier 5, the inverters 6 and 7, the integrator 8. The device operates as follows. : In the multiplication mode of two voltages, the inputs of the first and second non-rand are fed to the factors x (t) and y (t), to the input of the third operand Z (t) to the reference voltage, to the control inputs to the direct inputs the pulses U ,, 2 and Uj (see Fig. 2), which control the switching of the switches 1,2 and 3,4. The field voltage of the reference voltage 11 ,, is selected from the condition of providing negative feedback covering the multiplier 5 through the integrator 8 and the switches 2 and 4. When shown in

. K, j a „„ + a, ox (t) +

Uu

+ ap, x (t) + a ,, x (t) y (t) + aj, x (t) + + (t) dt,

(2) FIG. 2 control signals polarity Ujjn should be negative. The cycle of operation of the circuit consists of four equal cycles of the duration. The transformation of multiplier 5 can be represented as the first six terms of the expansion in the Maclaurin series of functions of two variables 2 00+ + ауy + а ". xy + + + Experiments show that such a decomposition rather accurately describes the real characteristic of the multiplier. We use the accepted mathematical model of the multiplier and determine the output voltage of the device, assuming that the input signals change very little during the cycle time. In the first cycle, the inputs x (t) and y (t) are connected to the inputs of the multiplier 5, and the output of the multiplier is connected to the integrator 8 directly. Taking into account that the function of transforming the multiplier is determined by expression (1), the change in the voltage on the integrator during this interval will be

Claims (1)

where K and is the integrator constant; T - switching period of the switches 3,4. In the second cycle, the signals are connected to the inputs of the multiplier 5, and (t), where p (t) is the voltage at the output of the integrator 8. The output of the multiplier 5 is connected to the integrator 8 directly, and the voltage change on the integrator is equal to KU j а - а, „and, ПЧ + ao, (. T) - а„ Uon | 3 (t) +, In the third cycle the input signal y (t) is connected to the first input of the multiplier 5, the input signal x is connected to the second one (t) via inverter 6, the multiplier output is connected to integrator 8 via inverter 7. The voltage variation on the integrator during the third cycle will be equal to Ci (–a + a, –x (t) Ш ao, y (t) + a „ x (t) y (t) a, oX (t) - a “y4t) dt. the signal ft (t), to the second - the input signal Uj ,,, through the inverter 6, the output of the nipper 5 is connected to the integrator 8 through the inverter 7. The change in voltage across the integrator during this cycle will be equal to, K, j - a - ao, (t) - a „and„ „p (r) / (t) dt. o The output voltage of the integrator t) will change until the average value of the increment during the integration time is zero, i.e. in the established mode iiU, + U2 + li, + & U4 о) - а.and „+ а„ x (t) y (t) - а „Uonp, (t) where the bar above means averaging over a quarter of the switching period of the re - switches 3 and 4. Since it is assumed that during the period T all signals change little and B (t) fl, then ft - x (t) y (t). a. (M | jj.p - t- (UOR a ,, Uon From expression (7) it is obvious that the steady-state output voltage of the device at quasi-constant voltages x x (t) and y (t) does not depend on additive a, neither from the multiplicative tia, errors of the original signal multiplier, nor from the constant time of the integrator. The output voltage is also not affected by the component errors, which are proportional to the even powers of the input signals of the multiplier 5 and linearly through one from the inputs of this multiplier. The resulting error of this device is determined by the instrument The use of modern element base allows the comparative simplicity of the device to carry out the multiplication operation in accordance with the accuracy class of 0.1 at a switching frequency of 1000 Hz based on multipliers of 52511С2Б class 2.0. From expression (7) it is obvious that if instead of the reference voltage U to the input Z (t) to give a signal, then the output „x (t) y (t) NOA is the signal of the device p; - / h, i.e. it is possible to work in the mode of dividing the product of two signals by the third. In addition, if the input voltage Z (t) is applied from the device output, Toj3 (, - x (t) y (t)). Thus, the proposed device significantly reduces the influence of the main components of the errors of modern integrated signal multipliers and allows use integral multipliers without external adjustments Formula of the invention Analog computing device containing a multiplier, the output of which is connected to the first input of the first switch and the input of the first inverter, the output of which is connected to the second input of the first switch A connector whose output is connected to the integrator input, whose output is connected to the first input of the second switch and is the device output, the second input of the second switch is the input of the first operand of the device, and the output is connected to the first input of the multiplier, the second input is connected to the output The third switch, the control input of the first switch is connected to the control input of the third switch and is the first clock input of the device, characterized in that, in order to increase the obesity of the device TWA, the second inverter and the fourth switch are entered into it, the first and second inputs of which are the inputs of the second and third operands, respectively, the output is connected to the first input of the third switch and the input of the second inverter whose output is connected to the second input of the third switch, the control input of the second the switch is connected to the control input of the fourth switch and is the second clock input of the device.