SU1307540A1 - Polyfunctional clocked flip=flop - Google Patents

Abstract

The invention relates to computing and can be used in automation devices, in devices for receiving and processing information. The purpose of the invention is to increase reliability. To achieve this goal, the element NOT 9 is entered into the device. The device also contains inputs 1-5, elements NOT 6,7,8, .. elements OR NOT 10-18, outputs 19,20. This trigger implements the functions of DV-, JK-, TV-, RS-, D-, T-triggers. Reliability of reliability is caused by a reduction in the number of external leads, 1 sludge. with (L with: with about vl sd

Description

The invention relates to computing and can be used in automation devices, in devices for receiving and processing information, automatically measuring parameters, controlling and controlling processes in instrumentation.

The aim of the invention is to increase reliability by reducing the number of external leads.

The drawing shows a diagram of the multifunction clocked trigger.

A multifunction clocked trigger with clock cut-off control realizes the functions of DV-, JK-, TV-, RS-, D-, T-flip-flops and contains five inputs 1-5, four elements NOT 6-9, nine elements OR- NOT 10-18 and two outputs 19 and 20. The first input 1 is a tuning input, the second and third inputs 2 and 3 are information inputs, the fourth input 4 is information tuning, the fifth input 5 is clock, the first output 19 is its direct output, the second output 20 of the flip-flop is an inverse output.

Multifunction trigger works as follows.

The eighth and ninth elements OR-NOT 17 and 18 constitute a bistable cell (an asynchronous RS flip-flop with direct inputs) with outputs 19 and 20, and the elements NOT from the first to the fourth 6-9 and the elements OR-NOT from the first to the seventh 10-16 form the control circuit of the multifunctional trigger.

In the control circuit consisting of elements 6 through 16, the following functions are implemented at the outputs of the elements OR NOT: at the output of the first element OR NOT 10

Z, at the output of the second element OR NOT 11

g at the output of the third element OR NOT 12

Z J- X2X :). R it

at the output of the fourth element OR NOT 13

Z XjQR;

at the output of the fifth element OR NOT 14

 Z, Z3Z4S (X,) - () A

() (XjQR) -S.

The output of the string element OR NOT 15 forms the input R of a bistable cell, therefore:

  (Z, VZ2VZ3VCVS) (X X3X RVX X2QRvXj, X RvX5QRvCVS) (R- (X ХзХ УХ X руХгХ. XjQ) vCvS)

C -S (RVCX. V XjQ)). The output of the seventh element SHS-NOT 16 forms the input S of a bistable cell, therefore:

25

thirty

. (C) ((X.X,) - (X, X-, QR) v KX2X4R) (X5QR) .SVC)

c (SVR (X, XjX. V x. V X2X4Ux sp)). Denote by F the function entering into the expressions for R and S and equal to

F X X2Qv x XjX4V, then we get

(FVR)

VR), 1 RVS) J

0

(F-RVS) J (1)

Taking into account the expressions obtained, the operation of the proposed trigger in time can be described as follows.

When the value of the clock signal C 1, the output signals of the control circuit based on expressions (1) take the values:

 §- (FVR) 0; (F RVS) 0.

45 Therefore, j, until, the values of the output signals Q and Q at the outputs of the bistable cell remain unchanged (storage mode). When the clock signal 50 is switched from one to zero (i.e., cut off from signal C) at the first moment, the signals R and S retain their former values, and at a later moment their values are determined in accordance with

55 (i) as:

 (FVO); (F-OVO) F.

clock signal C from one to zero, the output signals of the control circuit S and R (and hence the output signals of the bistable cell Q and Q) take values in accordance with the value of the function F.

Depending on the value of the function, there are two possible ways to operate the circuit.

If, then,.

If, then,.

After switching the values of the output signals of the control circuit S and R from the state (0,0) to the state (1.0) or (0.1) before the end of the value of the clock signal, the values of the output signals of the control circuit S and R (a hence the value

the output signals of the bistable cell Q and Q) remain unchanged even if the information inputs X., X, X2, Xd are distorted due to the influence of interference signals.

Indeed, if, then at subsequent times in accordance with (1)

, (FVR) 6-T- (FVO) 0-,

() 6- (F-OV1) 1. If, SfO,, then at subsequent times

(FYR) 6-0 - (FV1) 1; (F-RVS) 0- (F-TVO) 0.

Consequently, at subsequent times after switching over, the values of the signals 8 and R are preserved without change, regardless of the values of the output Q and X of the sixth element OR NOT HE, signals X,.,., X determining the output of the fourth element OR NOT a function of function F.

one with the fourth inputs of the fifth and sixth elements OR NOT, the fifth input of the trigger is connected to the fifth one. Thus, the proposed scheme implements a timed trigger with control by the cut of the clock signal - 5 TO the sixth element OR — NOT and the first input of the seventh element OR NOT, setting up the multifunctional move of the fifth element OR — NO is connected to the trigger for implementing one or another function of the second input of the seventh element of the function in accordance OR. NO, the output of the sixth element OR is with the table by changing the function 50 NOT connected It is with the fourth input of the first F in expressions (1) with the corresponding element ILY NOT, the second input of the switching inputs X, ..., X.

At the first setting, the function F takes the value F JQVKQ, which corresponds to the JK-flip-flop operation, with the second 55 with the first input of the eighth setting element, which corresponds to OR-NOT, the output of the seventh element OR-working DV-trigger, at the third setting - (VVT) Q that corresponds to the TV-trigger, with the fourth element OR-NOT, the third input of the third element OR-NOT, the second input of the fourth element OR-NOT and

NOT connected to the fifth input of the fifth element OR-NOT, the sixth input of the sixth element OR-NOT and the first input

corresponds to the RS-flip-flop operation, provided that the combination of input values is prohibited, with the fifth setting, which corresponds to the B-flip-flop operation, and at the sixth setting, the F function TQVTQ, which corresponds to the T-flip-flop operation.

Therefore, the proposed trigger can be configured to implement any functions of JK-, DV-, TV-, RS-, D-, and T-flip-flops.

Claims (1)

Invention Formula A multifunction clocked trigger with a clock cut-off control containing three elements NOT and nine elements OR NOT, the first input of the trigger is connected to the first input of the first element OR NOT and the input of the first element NOT, the output of which is connected to the first input of the second element OR- NOT, the second input of the trigger is connected to the first input. the third element OR NOT, the third input of the trigger is connected to the first input of the fourth element OR NOT, the fourth input of the trigger through the second element is NOT connected to the second inputs the first and third elements of the STI-NOT, the output of the third element is NOT connected to the third input of the first element OR NOT, the output of the first element and the sixth element SHS-NOT, the output of the second element OR-NOT connected to the second inputs of the fifth and sixth elements OR-NOT, the output of the third element OR-NOT connected to the third inputs of the fifth and sixth elements OR-NOT the output of the fourth element OR-NOT co one with the fourth inputs of the fifth and sixth elements OR — NOT; the fifth input of the trigger is connected to the fifth input of the fifth element — OR — NOT connected to the second input of the seventh element OR — NOT, the output of the sixth element OR — NOT connected to the fourth input of the first the second element with the first input of the eighth element OR NOT, the output of the seventh element OR- the second element OR NOT, the third input of the third element OR NOT, the second input of the fourth element OR NOT and with the first input of the eighth element OR NOT, the output of the seventh element OR- NOT connected to the fifth input of the fifth element OR-NOT, the sixth input of the sixth element OR-NOT and the first input 513075406 the ninth element OR NOT, the output of the eighth number of external conclusions, in one element is NOT connected to the first OR element, a trigger output is output and the second trigger input is connected to the second input. the input of the ninth element OR NOT, you are the input of the fourth element NOT, the output the stroke of which is connected to the second output of which is connected to the third input trigger house, the third input of the fourth-second element OR NOT, the third entrance of the element OR NOT and the second input of the trigger is connected to the input of the third of the eighth element OR-NOT, about tl and -element NOT, the output of the eighth element is the fact that, with the goal of OR-NOT connected to the fourth, increasing the reliability due to the contraction of the second element OR-NOT.