SU1305814A1 - Polyphase quasisine voltage generator - Google Patents

Abstract

The invention relates to electrical engineering and can be used in frequency converter control circuits. The aim of the invention is to simplify and extend the functionality. Under the action of clock pulses fed to the input of counter 2, the latter generates a binary code that is addressable to the permanent storage device and, i (L 00 o 00 00 I

Description

130

3, in which codes of discrete samples of sinusoidal voltage are recorded and on which the code sequence is formed, transformed into a stepwise quasi-sinusoidal voltage. The binary code from the outputs of counter 2 also enters the first input port of the adders of 6 channels forming the output voltage of each

one

The invention relates to a converter technique and can be used in frequency converter control circuits.

The aim of the invention is to simplify the generator and extend the functionality.

FIG. 1 shows a functional diagram of the generator; Fig. 2 shows timing diagrams explaining the operation of the circuit; FIG. 3 shows a programming table for the persistent storage devices.

The generator contains serially connected control generator 1 of clock pulses and counter 2, the number of channels forming the phases of the output voltages of the permanent storage device 3 and digital-analog converters 4, the inputs of which are connected to the outputs of the permanent storage device 3, the channel of the formation of the output voltage of each subsequent the phases are additionally equipped with a setting device 5 of the code and an adder 6, the inputs of the first port of the adder are connected to the outputs of the counter and the inputs of the permanent storage device the first channel for the formation of the output voltage, and the inputs of the second port for the outputs of the code setter, the outputs for the inputs of the permanent memory devices for the formation of the output voltages of the subsequent channels.

The generator runs a trace;:, in a skinny way.

Under the action of the control voltage U |, the clock pulse generator 1 produces a pulse sequence with a frequency determined by the level of this voltage (curve U,

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of the subsequent phase, the second port of the inputs of which receives the code from the outputs of the setting units of the code 5 "In the units of the code -5, the given phase-shift codes are: similar voltages of other phases; As a result, the output voltages of other channels are formed with a phase shift relative to Channel One, 3 Il.

FIG. 2). Under the action of clock pulses at the input of the counter 25, the latter generates an increasing binary code at its outputs

(family of curves U, Fig. 2), which is addressable for the persistent storage device 3, in which codes of discrete samples of sinusoidal voltage are written (Fig. 3). 06constructed at the outputs of a constant

the memory code sequence (family of curves U, Fig. 2) is fed to the inputs of the digital-analog converter 4, as a result a stepwise quasi-sinusoidal voltage is formed at the output of the latter (curve U, fig. 2).

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The binary code from the outputs of counter 2 also goes to the nepBbrii port of inputs

adders 6 channels forming the output voltage of each subsequent phase, the second port of the inputs of which receives the code from the outputs of the setters 5 of the code. At the same time, codes for setting the phase shift of the output voltages of other phases are generated in the code setters. As a result of summation, the outputs of the adders 6 form addressable codes with a given phase shift.

For example, on the output voltage channel of the second phase, a code is formed at the output of the adder 6

a sequence (family of curves Uj, Fig. 2), which is fed to the inputs of the permanent storage device 3 of its channel. At the output of a permanent memory device

3 of this channel forms a code sequence (family of curves

Ug, FIG. 2), which is fed to the inputs of a digital-to-analog converter 4, at the output of which a stepped quasi-sinusoidal voltage is formed with a given phase shift (curve, fig. 2).

Similarly, the formation of the output voltages of other channels with a given phase shift in the channel relative to the output voltage of the first channel.

If necessary, the phase shift is changed by rebuilding the code in the unit 5 of the code without changing the truth table of the permanent storage devices 3.

Thus, the invention makes it possible to extend the functionality of the generator by providing a change in the phase shift by rearranging the code in the code master, while simplifying the construction of the generator in connection with the use of fixed memory devices with an identical truth table.

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Claims (1)

Claims of the invention A multi-phase quasi-sinusoidal voltage generator containing serially connected controllers with a 5 clock pulse generator and a counter, according to the number of channels forming the phases of the output voltages, permanent memories and digital-analog converters, inputs About which are connected to the outputs of permanent storage devices with discrete sampling codes of sinusoidal voltage, characterized in that, in order to simplify and extend the functionality, it is provided in the output voltage shaping channel of each succeeding phase with a setting device and an adder, wherein the inputs of the first port of the sum20 mator are connected to the outputs of the counter and the inputs of the permanent storage device of the first channel forming the output voltage, and the inputs of the second port to the outputs of the setpoint generator, ode - to the inputs of permanent storage devices generating output voltages subsequent channels. 25 f (dpec rom l / FisFeF FtFi / aLuDGDL Editor O. Yurkovetska  Compiled by S.Stankevich Tehred A. Kravchuk Proofreader A.Zimokosov Order 1463/53 Circulation 661 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, F - 35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 breathing ROM a.J