SU1300490A1 - Device for simulating the queueing systems - Google Patents

Abstract

The invention relates to computing and can be used to simulate processes in queuing systems. The purpose of the invention is to expand ... functional capabilities by simulating a service interrupt for a wok. The device allows you to simulate the operation of closed and open QS with interruption and without interruption of service for the wok. Such QS can describe the operation of many of their systems operating in real time. An interrupt in the device is interpreted as an increase in the service time of the current application by the interruption time, which is a controlled variable and is preset. If, during the service time of the upcoming application, several applications arrived in the system, the service time of the current application is increased by the total time of interruption of all incoming applications. 5 il. yu (L "with

Description

The invention relates to computing and can be used to simulate processes in queuing systems.

The purpose of the invention is the expansion of functional capabilities by simulating the interruption of service charges.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 diagram of the shift block; in fig. 3- unit as shown in FIG. 4 is a diagram of a service enable signal generator; on 1FIG. 5 - block diagram interrupt.

The device (Fig. 1) contains a shift unit 1, a generator of 2 pulses, a reversible counter 3, a polling unit 4, an output unit 5, a controlled oscillator 6, a service resolution generator 7, a prohibition block 8, an interrupt unit 9.

FIG. 1 also indicates the start inputs 10 and the installation 11 of the device input 12 recording information.

Shift unit 1 is a non-standard version of the shift register, which is based on a standard bi-directional shift register with sequential and parallel entry of information,

Depending on the states of the installation inputs V, V, j and R block 1. can work in different modes:

sequential entry with a shift to the right, sequential entry with a shift to the left, parallel entry, storage, installation in O.

In the sequential-entry mode with information shifting to the right, the input level V is fed to the logic input level V - the lock level O

1. Parallel input of information occurs when the setup inputs are in the logical 1 state.

To determine the priority bit of the standard shift register, a set of elements AND 13, elements AND 14, elements OR 15 NOT and elements 16 is intended. The block 1 shift also includes the element OR 17 and the element NOT 18.

To quench 1, the priority bit of the standard shift register without changing the state of the remaining bits of this register is intended to be a combination of

50

five

ABOUT

five

Q

g

g

the United elements SHI-NOT 15, AND 16, OR 19, the delay element 20. They each implement the logic function XAyvxAy and have two inputs. For example, for the first bit, input X of the circuit is connected to the first output of the standard shift register 21, and its second input (input y) is connected to the output of the first And 13 element. The delay element is designed to ensure stable operation of the shift register 21 by eliminating constants.

The functional purpose of the inputs and outputs of the block 1 shift the following:

input C is the input receiving clock pulses from generator 2;

inputs for receiving the polling signals from the polling unit 4 and the control signal of the standard shift register - input V;

input D is the input of the demand from the controlled generator 6;

the output of the element OR NOT 16 is the output signal of the absence of the quota in the queue;

element bypass of OR-AND 15 - output of the wok supplied for servicing;

the output of the first bit of the shift register 21 is the output of the service incoming, but due to the presence of a queue of demand or no signal about the end of service of the previously received application queued for service (output of the 1st bit of the standard shift register);

the output of the 8th bit of the shift register is the output of a signal that the queuing time of the queued application is exceeded; this output removes the tickets from the queue due to the fact that their waiting time for services has exceeded the limit value.

Interrogation unit 4 (Fig. 3), designed to perform the interrogation of the bits of the standard shift register, contains a delay register 22, a trigger 23, a delay element 24, an OR element 25.

The output unit 5 performs the function of pulse extensions to a predetermined value for each of their inputs. Shaper 7 of the service enable signals (Fig. 4) contains the triggers 26 and 27, the AND-HE elements 28 and 29, the differentiating elements 30 and 31, the spreaders 32, 33 pulses and the OR element 34.

Interrupt unit 9 (FIG. 5) is designed to ensure the operation of the device in the interruption mode for servicing the request and contains a second AND-NE element 35, a delay element 36, a second reversible counter 37, a third OR element. 38, element OR-NOT 39, first element OR 40, first element-NOT 41, first reversible counter 42, second element OR 43, second element AND 44, switch 45, first element AND 46, trigger 47, sensor 48 code.

The reversible counter 37 is designed to count the number of interrupts that are not processed, and the counter 42 to set the time for one interruption. Input R serves to set the counter to O, input C to pre-record information into the counter. The installation of the counter in O takes place by a positive differential pulse at the input R, while the input C must be logic level 1. Pre-recording information into the counter

carried out at the inputs D.D

 h

negative impulse impulse input C, while the input R must be a logical level of O.

The trigger 47 serves to control the flow of pulses from block 2 to the subtractive input of the reversible counter 42 and to block 7 to generate a service enable signal.

The functional purpose of the inputs

and the output of block 9 interrupt following:

reception input for the wok from controlled generator 6;

input 12 pre-recording information of the device;

input receiving clock pulses from generator 2;

Input 10 is the triggering input of the device.

The device works as follows.

When modeling open-loop CMs from the installation input 11 of the device, the input of the block of prohibition elements 8 receives a signal prohibiting the passage of pulses from the output of the reversible counter 3 to the control input generator 6 for wok.

When simulating closed QS, signals are allowed to pass from the output of the reversible counter 3 to the control input of the generator 6 for

From the output of the generator 6 to the input of the shift unit 1, a stream of pulses arrives imitating the flow of the application in the QS. The intensity of this flow in the simulation of open QS remains constant. When simulating closed QS, the intensity of the flow of pulses varies depending on the number of applications in the system.

Information on the number of applications currently in the system is stored in the reversible counter 3.

Based on the information stored in the reversible counter 3 and fed to the control input of the generator 6, it is configured.

When simulating open and closed QS without interrupting service charges, switch 45 of interrupt unit 9 is in position I. Logic level 1 is applied to the second input of interrupt block element 44. The element is open. The pulses from the generator 2 are supplied to the unit 7 for generating the service enable signals.

When simulating open and closed CMCs with service interruption, switch 45 is in position II. The trigger 47 controls the flow of pulses from the generator 2 to the block 7 forging the service enable signals. Before starting work in this mode, the sensor 48 sets a binary number specifying the amount of time for one interrupt. At the input 12 of the pre-recording of information, an impulse is given, by the decay of which the inputs write binary information from the sensor 48 to the counter 42, and the impulse front delayed by the delay element 36 for the time of operation is counter 42, the element OR 43 and the counter 37, the last is reset. Subsequently, at the input 12, the logic level O is maintained, and the outputs of the counter 37 and the OR 38 element are at the logic zero level, and the logic level 1 is fed to the input of the trigger 47 from the output of the OR-NOT 39 element.

The trigger 47 is in a single state. Clock pulses from generator 2 can pass to block 7

to

generating the service enable signal and do not go to the subtracting input of counter 42.

The operation of the device begins with the fact that a stream of pulses arrives at the input 10, simulating the end of the service of one application and the possibility of starting the service of the next one. This signal enters the driver 7. A pulse is sent from the generator 6 to the shift register 21 and to the input of the block 9 interrupts. According to the positive differential of the clock pulse from the generator 2 (it EIs the current time) f5, the incoming signal in the imaging unit 7 (Fig. 4) passes a link of elements 26, 28, 30, 32, is supplied (Fig. 1) to the reversible counter 3 and to the block 5 output. At the same time, the same signal, 20 passing the OR 34 element, triggers polling block 4 (FIG. 2), which outputs a logic level O to input 1 of shift register 21 (FIG. 2), and polling signals 25 (logical 1) come from information outputs to input elements And 13 knots. In block 1 of the shift, in the presence of an impulse of a request for a positive differential of the clock pulse from generator 2, a unit is recorded in the reversible counter 37 of the interrupt block (Fig. 5). The trigger 47 is in the state 1, the element AND 44 is open, the clock pulses from the block 2 are passed to the shaper 7.

Simultaneously with writing 1 to the reversible counter 37 of the interrupt block in the shift block 1 (Fig. 2), sequential 40 loading 1 is shifted to the right, and from the outputs of the elements 2 the binary information in the parallel code comes to determine the priority bit of the standard shift register ( this 45 will be the first in order, starting with the eighth, the bit containing the logical 1),

13004906

versable counter 3 and from the senior eighth bit to block 5 of the output.

After servicing the application, triggering input 10 receives a signal simulating the possibility of starting servicing the next application, which sets the trigger 26 of the formation unit to state 1, and the trigger 47 of interrupt unit (Fig. 5) goes to state O. Element I 44 is closed block 7 is terminated; the service enable signal is not received by the polling unit. The input element AND-NOT 41 with the inverse output of the trigger 47 receives the level of logic 1, the clock pulses describe the contents of the counter 42.

When the contents of counter 42 become equal to zero, the negative potential drop at the output of the element OR 43 is fed to the input of the counting counter 17, reducing its content by 1, and is also fed to the synchronization input of counter 41 and the binary number is again recorded from its sensor 48 specifying the time of interruption.

Thus, the time of one interruption is determined by the formula

t t, in,

where t is the time of one interruption; T - period of clock pulses

served on subtractive

counter input 42; B is the binary number supplied

from sensor 48.

If, during the time of servicing the current application, several applications arrived in the system, then the service time of the current application is increased by the total time of interruption of all incoming applications.

When writing the number to the counter 42, the logical 1 appears at the output of the G1 43, which through the element OR 40 enters the input C of the counter 42.

When writing the number to the counter 42, the logical 1 appears at the output of the G1 43, which through the element OR 40 enters the input C of the counter 42.

The process of writing off information is resumed until the contents of counter 37 are equal to zero, which means the end of the interrupts. At the output of the set priority 50 bit, an impulse (for application) through the OR element 17 is charged for servicing. Thus, the service with the longest waiting time is selected for servicing (discipline First 55 elements OR-NOT 39 comes - first served). Also, the logic level is 1. Trigger 47 pulses arrive, respectively, in state 1 and after the first low-order bit, the clock pulse standard goes to block 7 of the VOU to register output block 5 and is updated. The enable signal of the block 7 is terminated; the service enable signal of the next request is not received at the polling unit. The input element AND-NOT 41 with the inverse output of the trigger 47 receives the level of logic 1, the clock pulses describe the contents of the counter 42.

When the contents of counter 42 become equal to zero, the negative potential drop at the output of the element OR 43 is fed to the input of the counting counter 17, reducing its content by 1, and is also fed to the synchronization input of counter 41 and the binary number is again recorded from its sensor 48 specifying the time of interruption.

Thus, the time of one interruption is determined by the formula

t t, in,

where t is the time of one interruption; T - period of clock pulses

served on subtractive

counter input 42; B is the binary number supplied

from sensor 48.

If, during the time of servicing the current application, several applications arrived in the system, then the service time of the current application is increased by the total time of interruption of all incoming applications.

When the number is written to the counter 42, the logical 1 appears at the output of the GUT 43, which through the element OR 40 enters the input C of the counter 42.

The process of writing off information is resumed until the contents of counter 37 are equal to zero, which means the end of the interrupts. The logic level 1 appears at the output of the OR-NOT 39 element. The trigger 47 goes to state 1 and the passage of clock pulses to block 7 is renewed. The service enablement signal of the next application enters the polling unit. Thus, the interrupt block extends the service time of the current request by the time of the interrupt.

After the survey, by the bloy 4.

input V

standard register

(FIG. 2) the logical level 1 (the logical level 1 is constantly maintained at the input V).

In the node of the shift unit 1, the inputs of the elements 15 are supplied respectively with binary information from the outputs of the elements AND 13 and the bit outputs of the register 21. As a result, the inputs of the shift register 21 in the parallel input mode contribute to all bits of information without change except for the priority bit, in which logical 1 is zeroed, i.e. logical 1 priority bit is suppressed.

If at the moment of polling block 1, the shift is empty, a signal is received through the element IL-NOT 18 to shaper 7 in order to repeat the poll in the next cycle. If there is a positive difference in the clock pulse, this signal passes the link of the elements 27, 29, 31, 33 and enters the output unit 5 and simultaneously triggers the interrogation unit 4 through the element 34.

During operation of the device, pulses are continuously applied to the reversible counter 3: to the summing input — from the lower bit of the standard shift register (the number of applications entering the service), to the subtracting input — from the generator 7 (the number of serviced applications). Therefore, at any time in the reversible counter 3 there is information on the number of applications that are in the system.

Thus, the proposed device makes it possible to simulate the operation of closed and open QS with interruption of service of the application.

Claims (1)

Invention Formula A device for simulating queuing systems comprising a shift unit, a clock pulse generator, a controlled oscillator, a reversible counter, a block of bar elements, a poll unit, a block five 0 five 0 five the output, the service resolution signal generator, whose information input is connected to the no-fault signaling output in the shift block queue, the clock input of which is connected to the first output of the clock generator, the shift control input and the group of information inputs of the shift block are connected to the outputs of the polling unit, information the input of which is connected to the exit resolution of the polling generator of the service enable signals, the exit end of the service which is connected to the subtractive input I reversible counter and first the input of the output block whose outputs are the outputs of the device, the second, third and fourth inputs of the output block are connected respectively to the output of the first bit, the output of the last bit and the output of the shift block service call, the output of the first bit of which is connected to the summing input a reversible counter, the bit outputs of which are connected to the information inputs of the prohibition block, the control input of which is the control input for the operating mode of the device, the group of outputs of the block of bar elements and respectively is connected with a frequency control input start yn .ravl emogo requisition generator whose output is connected to an input for receiving a wok shift unit input device start is the start input signal shaper authorization service, the absence of an alarm output In the queue, the queue is connected to the fifth input of the output unit, characterized in that, in order to expand its functionality by simulating service interruption, it additionally contains a block of interrupts consisting of two reversible counters, a trigger, two NAND elements, two AND elements, three OR elements, an OR-NOT element, a switch, a code sensor and a delay element, the input of which is connected to the pre-recording input in-. the formation of the device and the first input of the first OR element, the output of which is connected to the input of the first reversible counter, to the subtractive input of which the output of the first NAND element is connected, the summing input of the first the reversible counter is connected to the single potential bus, the discharge inputs of the first reversible counter are connected respectively to the code sensor outputs, and the setup input of the first reversible counter is connected to the zero potential bus, the discharge outputs of the first reversible counter are connected respectively to the inputs of the second element OR, the output which is connected to the second input of the OR element and the subtractive input of the second reversible counter, the clock input of which is connected to the potential potential bus, summing the input d is connected to the output of the second NAND element, the first input of which is connected to the output of the controlled generator of the device, the installation input of the second reversible counter is connected to the output of the delay element, and the bit outputs of the second reversible counter are connected to the corresponding inputs of the third element OR, f and . FIG. one 5 JO 00490 the output of which is connected to the first input of the first element AND and the input of the element OR NOT, the output of which is connected to the first input of the trigger, the first output of which is connected to the first input of the first element NAND, the second input of which is connected to the second input of the second element NAND, with the output of the clock generator of the device and with the first input of the second element I, the output of which is connected to the clock input of the generator of the signal for enabling the maintenance of the device, and the second input of the second element I is connected to the switching output of the switch the body, the first terminal of which is connected to the wider unit potential, and the second output of the switch is connected to the second output of the trigger, the second input of which is connected to the element I, which is connected via a cable TVA, 15 20 with the output of the par- the second input with the input of the run KctfemvuKyi CJ SILT S K6fftfKt / 7 tpepMt / pottffa /  To block S To Exit I FIG. 3 FIG. If H1 sh- 37 " 3 39 W W I Ogeneprrag KS / iOKf / 7 Compiled by V. Fukalov Editor M. Kelemesh Tehred M. Khodanych Order 1151/49 Circulation 673 VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 K5loku 5 WITH 39 J-1 I ifi-j g riT 4 -f 1 jtj g4Y ML 2 - W W I 7 41 (pt / ". 5 Corrector L, Patay Subscription