SU1300457A1 - Device for comparing two n-bit binary numbers - Google Patents

Abstract

The invention relates to the field of automation and computing. The purpose of the invention is to reduce hardware costs. To this end, each intermediate cell of the device contains two AND-OR-NOT elements, the outputs of which are connected to the outputs of the corresponding AND-NOT elements. The output cell contains four AND-OR-NOT elements and five AND-NOT elements, the input cell contains three AND-NOT elements. The hardware costs of selling the device on the widely used IC-155th, 176th series is 1 IC case for discharge 5 or 3 tab. j: SP

Description

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The invention relates to automation and computer technology and can be used in the construction of computer control and monitoring devices.

The purpose of the invention is to reduce hardware costs.

Fig, 1 shows a diagram of the proposed device; figure 2 - diagram of the first cell device; FIG. 3 is a diagram of the i-th cell of the device, where i 2,3, ..., (p / 2-1); Figures 4 and 5, the n / 2 cell, embodiments.

The device contains p / 2 cells 1 ,, 1 4,. 1 h / g and each f-cell, where f-2,3, ..., p / 2, contains the first, second, third, fourth inputs 2g - 5g, and each j-cell Ij, where j 1,2 , .. i, (n / 2-l), contains the first, second, third and fourth outputs 6; - 9: of the transfer, which are connected respectively with the inputs 2i, - Sj + t of the transfer (+ 1) cell Ij4i n / 2 - the cell contains the first and second outputs 10 and 11 of the result, which are the outputs of the device.

Each cell has a 12j input of the direct value (21-1) of the first digit, an input 13g of the inverse value (21-1) of the second digit of the second digit, an input of I4g of the inverse value () of the first digit, input 15g straight value (2t-l) -ro bit of the second number, input 16g inverse bit value of the first number, input 17 straight value 2f-ro bit of the second number, output 18g straight value 2E-th bit of the first the numbers and the 19fi input of the inverse value of the second number of the first number The first cell has inputs 12, 13, 16 - 19, the functionality of which is analogously to to the entrances of the th cell.

The first cell 1 contains the first, second and third elements AND-NOT 20-22, the i-cell contains the first, second, third and fourth elements AND-NOT 26 and the first and second elements AND OR-NOT 27 and 28. n / 2 - the cell contains the first, second, third and fourth elements of AND-NO 29 - 32, as well as the first, second, third and fourth elements of AND-OR-NO 33-36.

The device works as follows.

Corresponding signals are applied to inputs 12-19 of all cells 1 with a cc00457 2

numbered numbers, the first bit being the youngest and the nth being the most significant.

The first cell 1 analyzes the ratio of the first and second bits.

5 compared numbers. The operation of this cell is illustrated in Table 1 (x is an arbitrary signal value). Outputs 6 - 9; -and cells 1 produce a code that depends (in the order of prioritizing theta): on the ratios 2i-ro bit of the compared numbers on the ratio (21-1) -th digit, on the code on the inputs 2 - 5; . The operation of this cell. Illustrates the TC table. 2

 According to Tables 1 and 2, codes 1100, 1101, and 1110 at the outputs of the transfer 6j-91 of each j-th cell Ij mean that A is c B (A is the first one being compared, B is the second), codes 0101, 0110,

20 1001 and 1010 - that, codes 001, 0010, OOP, 0111, 1011 and 1111 - that.

n / 2-cell D / 2 can be performed in two versions. The values of the signals at the outputs 10 and 11 of this cell depend on the ratio of the n-th, (n-1) -th bits of the numbers being compared, and on the code at the carry-over inputs 2π | 2., Zn / 2.4 "/ and Snf-i of this cell, and according to the first variant, code 10 at outputs 10 and 11 means that A B, code 00 - that, code O - that A B. According to the second embodiment of this cell, the ratio corresponds to code 11.

35 Work n / 2 cell 1 (Table 3 illustrates the two options.

Formula of invention

 A device for comparing two n-times random binary numbers containing p / 2 cells, the first cell containing the first, second and third AND-NOT elements, and the input of the second bit of the second number of the device is connected to the first input of the third element AND -NON, whose output is connected to the first input of the second NAND element, the outputs of the first and second NAND elements are, respectively, the first and second cell transfer outputs, i, the cell, where i 2,3, ..., (n / 2-l), contains the first, second, third and fourth elements

55 AND-NOT, with the first and second inputs of the transfer of this cell connected to the first inputs of the first and second elements AND-NOT, respectively, the outputs

which are connected to the first inputs of the third and fourth elements AND-NOT, respectively, the outputs of which are respectively the first and second outputs of the transfer of this cell, n / 2- from the cell contains the first, second, third and fourth elements AND-NOT, and the first transfer input This cell is connected to the first input of the first element of the N – N cell of the n / 2 cell, the input of the direct new value of the nth digit of the first number of the device is connected to the first input of the third cell of the C – N cell of the n / 2 cell, output which is connected to the first input of the fourth element AND – NOT n / 2 ki, the output of the second element NAND – n / 2 cell is connected to the second input of the fourth element NAND – N n / 2 cell, the output of which is the first output of the n / 2 cell, first, second, third and the fourth transfer of the j-th cell, the first, second, third and fourth transfer of the j-th cell, where

with the first, second, third and fourth inputs of the first AND-IL element of the ith cell, the output of which is connected to the second inputs of the first and second AND-NO elements of the same cell, the direct value of 2i-ro bit of the second device , the input of the inverse value of the 2i-ro bit of the first chi device, the input of the inverse value of the (2i-l) -ro bit of the first number of the device, and the input of the direct value of the (21-1) th digit of the second number of the device of the second number of the first, second, third and fourth J5 inputs of the second AND-OR-NOT element of the ith cell, the input of the inverse 2i-bit value The second number of the device is connected to the third output of the transfer of the i-th cell, the input of the direct value 2i-ro bit of the first number of the device is connected to the fourth transfer output of the i-th cell, n / 2-cell contains the first, second, third and fourth AND-OR-NOT elements

20

 , 2 ,. .., (n / 2-l) are connected according to t-25, the first transfer input n / 2

With the first, second, third, and fourth transfer inputs of the (C + 1) cell, the first and second outputs of the n / 2 cell result are device outputs that are different from 30, so that, in order to reduce hardware costs, the input of the inverse value of the second bit of the second number of the device is connected to the third transfer output of the first cell, the input 35 of the direct value of the second bit of the first number of the device is connected to the fourth transfer output of the first cell, the input of the inverse value of the second

the cell is connected to the first input of the first element AND-OR-NOT n / 2 cell The second input of the transfer n / 2 cell is connected to the third inputs of the first element AND-NOT and / 2 cell and the first element AND-OR- NOT n / 2 cells, third transfer input of n / 2 cells, fourth transfer input of n / 2 cells, input of direct value (nl) -ro bit of the first number of the device and inverse value (nl) The -ro bit of the second number of the device is connected respectively to the first, second, three and fourth inputs of the second el

bit of the first number of a co-40 cop device AND-OR-NOT n / 2 cells, output

dinene with the second input of the third element AND-NOT the first cell, the output of which is connected to the first input of the first element AND-NOT the first cell,

which is connected to the second and fourth inputs of the first element of the AND-OR-NOT n / 2 cell, the input of the direct value of the n-th digit of the second number of the device — the input of the direct value of the first bit — 45 VA, the input of the inverse value of the n-th the first number of the device and the input number of the first number of the device, the input of the inverse value of the first bit of the inverse value (nl) -ro bit of the second number of the device connected to the first number of the device and the input pr - the second inputs of the first and second elements AND-NOT first cell, respectively, i-cell contains the first and Torah the AND-OR-NO element, wherein the third carry input, a fourth input transfer, direct input values (21-1) th discharge a first number

50

The second (nl) -ro bit of the second number of the device is connected to the first, second, third, and fourth inputs of the third AND-OR-NOT n / 2 cell, respectively, the output of which is connected to the second inputs 55 of the second AND-NOT element n The 2nd cell and the fourth element of the AND-OR-NOT n / 2 cell, the input of the inverse value of the nth digit of the second number of the device and the input of the inverse value (21-1) of the second digit of the second number of the device are connected respectively

from JO 004574

with the first, second, third and fourth inputs of the first element AND-OR-IS of the i-th cell, the output of which is connected to the second inputs of the first and second elements of the IS-NE of the same cell, the input of the direct value 2i-ro bit of the second number of the device , the input of the inverse value of the 2i-ro bit of the first device number, the input of the inverse value of the (2i-l) -ro bit of the first number of the device and the input of the direct value (21-1) of the second digit of the second number of the device are connected respectively to the first, the second, third and fourth J5 inputs of the second element AND-OR-NOT of the i-th cell, the input inver the 2i-ro bit value of the second number of the device is connected to the third transfer output of the i-th cell, the direct 2i-ro bit input of the first number of the device is connected to the fourth transfer output of the i-th cell, n / 2-cell contains the first, the second, third and fourth elements AND-OR-NOT,

20

the cell is connected to the first input of the first element AND-OR-NOT n / 2 cell, the second input of the transfer n / 2 cell is connected to the third input of the first element AND-NOT and / 2 cell and the first element AND-OR- NOT n / 2 cells, third transfer input of n / 2 cell, fourth transfer input of n / 2 cell, direct value input (nl) -ro bit of the first device number and inverse value input (nl) - The ro bits of the second number of the device are connected respectively to the first, second, third and fourth inputs of the second electromy connected to the second and fourth inputs of the first element. a AND-OR-NOT n / 2 cells, the input of the direct value of the n-th digit of the second number of the device, the input of the inverse value of the n-th bit of the first number of the device, the input of the inverse value (nl) -ro bit of the first number of the device and the input pr -

The second (nl) -ro bit value of the second number of the device is connected to the first, second, third and fourth inputs of the third AND-OR-NOT n / 2 cell, respectively, the output of which is connected to the second inputs of the second AND-NOT element n / 2nd cell and fourth element AND-OR-NOT n / 2 cell, the input of the inverse value of the n-th bit of the second number of the device;

dinene with the second input of the third element AND-HE of the n / 2 cell and with the third input of the fourth element AND-OR-HE n / 2 of the cell, the output of which is the second output of the result of the n / 2 cell, the direct input the value of the n-th bit of the first day of the device is connected to the fourth input of the fourth AND-OR-NOT element, n / 2th cell, you

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one

OO

01

1O i1

Xx

Xx

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01

1O 11

A B A B A B A B A B A A B A B

004576

the moves of the first element of the NAND – N / 2 cell and the first element of the AND – OR – N n / 2 cell are connected to the first inputs of the fourth element, respectively, of the AND – OR – N – 2 cell and the second element NI of the n / 2th cell or, respectively, of the second element of the NI-N, n / 2th cell and the fourth element of the AND-OR-NI n / 2th cell, w I

Table 1

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and

II

II

1010 1110 0010 ITO 1100 hhp 1001 1101 0001 0101

table 2

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10 Continued table. 2

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Compiled by V. Berezin Editor A. Ogar Tehred I. Popovich Proofreader E. Roshko

Order 1149/47 Circulation 673 Subscription

VNIIPI USSR State Committee

for inventions and discoveries, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, Projecto st., 4

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Claims (1)

a device for comparing two p-times binary numbers containing p / 2 cells, the first cell containing the first, second and third AND-NOT elements, the direct value input of the second bit of the second number of the device being connected to the first input of the third AND-NOT element, the output of which is connected to the first input of the second AND-NOT element, the outputs of the first and second AND-NOT elements are respectively the first and second outputs of the cell transfer, the ϊth cell, where i = 2,3, ..., (n / 2 -l), contains the first, second, third and fourth elements AND NOT, with the first and second the transfer inputs of this cell are connected to the first inputs of the first and second AND-NOT elements, respectively, the outputs of which are connected to the first inputs of the third and fourth AND-NOT elements, respectively, whose outputs are the first and second transfer outputs of this cell, respectively, n / 2-nd cell contains the first, second, third and fourth AND-NOT elements, the first transfer input of this cell being connected to the first input of the first AND-element of the n / 2nd cell, the input of the direct 10th value of the ηth discharge of the first number of the device being connected to first entry the third element AND-NOT n / 2nd cell, the output of which is connected to the first input of the fourth element 15 AND NOT n / 2nd cell, the output of the second element AND-NOT η / 2nd cell is connected to the second input of the fourth element AND -NOT the n / 2nd cell, the output of which is the first output of the result of the 20th n / 2nd cell, the first, second, third and fourth outputs of the transfer of the jth cell, the first, second, third and fourth outputs of the transfer of the jth cell , where j = l, 2, ..., (n / 2-l) are connected, respectively, with the first, second, third and fourth inputs of the transfer (j + l) -ft cells, the first and second outputs of the result n / 2 the ith cells are the outputs of the device, characterized in that in order to reduce hardware costs, the input of the inverse value of the second bit of the second number of the device is connected to the third transfer output of the first cell, the input 35 of the direct value of the second bit of the first number of the device is connected to the fourth transfer output of the first cell, the input of the inverse value of the second digit of the first number of the so-40 device is dined with the second input of the third AND-NOT element of the first cell, the output of which is connected to the first input of the first AND-NOT element cells, 'the input of the direct value of the first bit is 45 and the first number of the device and the input of the inverse value of the first bit of the second number of the device is connected to the second inputs of the first and second NAND elements of the first cell, respectively, the i-th cell contains the first and second elements AND-OR-NOT, and the third transfer input, fourth transfer input, direct value input of the (2i-l) -th discharge of the first number 55 of the device and an inverse value input (2i-l) -ro of the discharge of the second number of the device are connected respectively to the first, second, third and fourth inputs by the first AND-OR-NOT element of the i-th cell, the output of which is connected to the second inputs of the first and second AND-NOT elements of the same cell, the input of the direct value 2i-ro of the discharge of the second number of the device, the input of the inverse value of 2i ~ ro of the discharge of the first number devices, the input of the inverse value (2i-l) -ro of the discharge of the first number of the device and the input of the direct value (2i-l) -ro of the discharge of the second number of the device are connected respectively to the first, second, third and fourth inputs of the second AND-OR-NOT i element -th cell, input of the inverse value of the 2i-ro discharge of the second number of devices The device is connected to the third transfer output of the i-th cell, the input of direct value 2i-ro of the discharge of the first number of the device is connected to the fourth transfer output of the i-th cell, n / 2 cell contains the first, second, third and fourth AND-OR elements NOT, and the first transfer input of the n / 2nd cell is connected to the first input of the first AND-OR-NOT element of the n / 2nd cell, the second transfer input of the n / 2nd cell is connected to the third inputs of the first AND-NOT cell n / Of the 2nd cell and the first AND-OR-NOT element of the n / 2nd cell, the third transfer input of the n / 2nd cell, the fourth transfer input of the n / 2nd cell, the input is direct of the value (nl) -ro of the discharge of the first number of the device and the input of the inverse value (nl) -ro of the discharge of the second number of the device are connected respectively to the first, second, third and fourth inputs of the second AND-OR-NOT element of the n / 2nd cell, output which is connected to the second and fourth inputs of the first AND-OR-NOT element of the n / 2nd cell, the input of the direct value of the ηth discharge of the second number of the device, the input of the inverse value of the ηth discharge of the first number of the device, the input of the inverse value (nl) - ro of the discharge of the first number of the device and direct value input of the (n-1) th discharge the second number of devices are connected respectively with the first, second, third and fourth inputs of the third ele-. ment AND-OR-NOT n / 2nd cell, the output of which is connected to the second inputs of the second element AND-NOT π / 2nd cell and the fourth element AND-OR-NOT n / 2nd cell, the input of the inverse value p- of the second digit of the second device number is connected to the second input of the third AND-NOT element of the n / 2nd cell and to the third input of the fourth AND-OR-NOT element of the n / 2nd cell, the output of which is the second output of the result of the n / 2nd cell, the input of the direct value of the nth discharge of the first number of the device is connected to the fourth input of the fourth element AND-OR-NOT, n / 2nd cell, the outputs of the first element And E n / 2-th cell and the first AND-OR-NO n / 2-th cell coupled to the first respectively fourth rows WMOs element 5 cop AND-OR-NOT! n / 2nd cell and the second AND-NOT element of the n / 2nd cell or, respectively, the second AND-NOT element of the n / 2nd cell and the fourth AND-OR-NOT element of the n / 2nd cell. 1P I Table 1 Art. but bit at Ml. and in Ratio AND NOT 22 AND NOT twenty AND NOT 21 Outputs 6,7,8,9 0 0 0 0 A = B 01 = 1 10 = 1 1 1 = 0 1010 0 one A b eleven n 10 = 1 1,110 one 0 A b II 11 = 0 11 = 0 0010 one one A = B II II 10 = 1 IT 0 one X X A b 1 1 = 0 0x = 1 0x = 1 1100 one 0 X X A b 00 = 1 1x = x 1x = x xxi 1 one one 0 0 A = B 10 = 1 10 = 1 11 = 0 1001 0 one A b eleven II 10 = 1 1101 one 0 A b II 1 1 = 0 1 1 = 0 0001 one one A b II and 10 = 1 0101 table 2 Art. time. and in ----- Ml time. and in Entry 2,3,4,5 Ratio ------ AND-OR-NOT 28 AND-OR-NOT 27 AND NOT 23 AND NOT 24 AND NOT 25 AND NOT 26 Outputs 6,7,8,9 one 2 3 four 5. 6 7 8 9 10 eleven 0 0 0 0 0001 A b 01 + 10 = 1 01 + 01 = 1 01 = 1 01 = 1 11 = 0 1 1 = 0 0010 0010 A b and 10 + 01 = 1 II II n II 0010 xx11 A b II 11 + 01 = 0 x0 = 1 x0 = 1 1 1 = 0 11 = 0 0010 0101 A = B 01 + 10-1 01 + 01 = 1 01 = 1 1 1 = 0 11 = 0 01 = 1 IT 01 10 eleven 10 + 01 = 1 I! II m eleven IT 1001 II 01 + 01 = 1 11 = 0 01 = 1 01 = 1 11 = 0 1010 1010 II 10 + 01 = 1 eleven n eleven eleven 1010 Continuation of Table 2 one g 3 four 5 6 7 8 9 <0 <1 1100 A b 01 + 10 = 1 00 + 01 = 1 11 = 0 1 1 = 0 01 = 1 01 = 1 1 1 10 1101 - and 01 + 01 = 1 II II II If I 1 10 1110 / If 10 + 01 = 1 It eleven II II 11 10 0 0 0 1 xxx and in 01 + 11 = 0 xx + 00 = x xx = x xx = x x0 = l x0 = l 11 10 0 0 10 xxx A b 01 + 00 = 1 xx + 11 = 0 xOOl xO = l 11 = 0 1 1 = 0 0010 0 0 eleven 0001 A b 01 + 01 = 1 01 + 10 = 1 01 = 1 01 = 1 11 = 0 11 = 0 0010 0010 fl 10 + 10 = 1 eleven II II ff 0010 xx 11 fl 11 + 10 = 0 x0 = l xO = l one! If 0010 0101 A = B 61 + 01 = 1 01 + 10 = 1 01 = 1 11 = 0 11 = 0 01 = 1 01 10 01 10 η It II II II II 01 10 1001 It 10 + 10 = 1 11 = 0 01 = 1 oi = i 11 = 0 1010 1010 It It II • tl II II 1010 1100 A b 00 + 10 = 1 1 1 = 0 1 1 = 0 01 = 1 01 = 1 1110 1 101 II 01 + 10 = 1 II fl II If 1110 1110 If 10 + 10 = 1 If II II II 1110 0 1 X x xxx A b 11 + xx = 0 xx + xx = x xx = x xx = x x0 = 1 x0 = 1 1100 10 X x xxx A b 00 + xx = x ‘ xx + xx = x xx = x XX = X XX = X XX = x xxl 1 T 1 0 0 0001 A b 10 + 10 = 1 01 + 01 = 1 01 = 1 01 = 1 1 1 = 0 11 = 0 0001 0010 ft 10 + 01 = 1 II 1f If II 0001 xxI ft 11 + 01 = 0 xO = l xO = i II II 0001 0101 A = B 10 + 10 = 1 01 + 01 = 1 01 = 1 11 = 0 11 = 0 01 = 1 0101 01 10 eleven 10 = 01 = 1 II ft and II 0101 1001 eleven 01 + 01 = 1 11 = 0 01 = 1 01 = 1 11 = 0 1001 1010 It 10 + 01 = 1 It It eleven II 1001 1100 A b 10 + 10 = 1 00 + 01 = 1 11 = 0 11 = 0 01 = 1 01 = 1 1101 1101 tl 01 + 01 = 1 H II II It 1101 1110 It 10 + 01 = 1 tl ft eleven It 1101 one 2 Π ~ “Ί F 1 ¹⁰ T ‘” 3 1 ⁴ one 0 1 xxx A b 10 + 11 = 0 xx + 00 = x xx = x xx = x x0 = 1 x0 = 1 1 101 one 10 xxx A b 10 + 00 = 1 xx + 11 = 0 x0 = 1 x0 = 1 11 = 0 11 = 0 0001 one eleven 0001 A b 10 + 01 = 1 01 + 10 = 1 01 = 1 01 = 1 11 = 0 11 = 0 0001 0010 II 10 + 10 = 1 AND AND II eleven 0001 xx 11 eleven 11 + 10 = 0 x0 = 1 x0 = 1 one! II 0001 0101 A = B 10 + 01 = 1 01 + 10 = 1 01 = 1 1 1 = 0 11 = 0 01 = 1 0101 0110 n 10 + 10 = 1 n eleven eleven eleven 0101 1001 eleven 01 + 10 = 1 11 = 0 01 = 1 01 = 1 11 = 0 1001 1010 n 10 + 10 = 1 one! II II and 1001 1,100 A b 10 + 01 = 1 00 + 10 = 1 1 1 = 0 11 = 0 01 = 1 01 = 1 1 101 1101 II 01 + 10 = 1 eleven n II It 1 101 1110 eleven 10 + 10 = 1 eleven and II If 1 101 1 1 h a X h β H Η I I SIX I I I CN1S eiw * HX Th * one about about about about 3 o one n about Λ - one -four one one about ιω one Th I am / ~ "1X cm one about £ £ <Ti i co one "Ma • IS one Μ one si one about about θιω one I am I am MX one about about 1 t I his > £> + £ £ four· »L§ co one •• W dis one • m "M SI 1 i Ms one <b— four ^B l one about Im I am I am about at I AM) about about X about X X ^: , 1 about about about about _ about about about *> · about about about about To CO about about to »· about about "Well M sc about and about about - * * * ·· 13 1300457 S * s: e I I SCH122 Continued Tab eMIS § Λ * * 4Ί I Π • IS 1— • e ”s *> IS tw -“ IX О * 11 о —IS fttn S3 Μ <ч о oo oo oo 1101 01 + 1001> * "I 1 I 1 I I I I I I I I I I I I I I I I I I I I 1 I I I I I I I I I I I I I I I I I I I I I I I I J I I I I I I I I I I I P / 1/2 13p / 2 ό ό ό o FIG. 2