SU1300456A1 - Programmable logic matrix - Google Patents

Abstract

The invention relates to the field of computing and can be used in control devices. The aim of the invention is to increase the reliability of the programmable logic array (CLM) due to the introduction of self-monitoring means. These means are two modulo two control units 8–9 modulo two for the AND 10 and OR I1 PLA matrices, as well as two buffer 12 and 15, two input 13 and 14, and one output 18 shift registers. These tools allow, in addition to the main operating mode of the PLM, which consists in converting input information into output information in accordance with programming of matrices I 10 and ШШ 11, to have three self-test modes: accelerated, refined, and complete. These modes differ in the timing of the self-test and the degree of fault localization. 1 il. cl

Description

The invention relates to computing and can be used in control devices.

The purpose of the invention is to increase the reliability of the programmable log of the environmental matrix (PLM) by introducing self-checking means into it.

The drawing shows the scheme PLA

PLA contains information inputs 14 - 1 y ,, information outputs 2, -

 TO

sync input 3, first 4 and

the second 5 control inputs, the output 6 of diagnostic information, the control output 7, the first 8 and the second 9 blocks. controls, the elements AND 10 and the elements OR 11, which are made in the form of matrices of communication elements, the first buffer 12, the first 13 and second 14 input and second buffer 15 shift registers, control block 16, multiplexer 17 and output register 18. The inputs of the parallel reception of information of registers 13 and 14 are information inputs 1 of the PLA. In this case, the inputs of one of the indicated registers (for example, register 13) are direct, and the other is inverse. Inverse outputs of the registers 13 and 14 are connected to the inputs of the 19 elements And 10,

those. with horizontal tires matri-Shch.1. The outputs 20 of the matrix 10, i.e. its vertical tires are connected to the inputs of receiving information from the registers 12 and 15 and to the inputs of the first control unit 8. Each j-th column of matrix 10 contains 2n communication elements (shown with tilted arrows pointing up) and forms a 2n-input element AND, the output of which is vertical bus 20j (j 1, m). The outputs of the register 15 are connected by the inputs of 21 elements OR 11, i.e. with vertical tires, outputs 22 of the matrix P, i.e. The horizontal buses of this matrix are connected to the information inputs of the output register 18. Each i-row of the matrix 11 contains m communication elements (shown with oblique arrows pointing down) and forms a t-input element OR, the output of which is horizontal bus 221 (, k). The outputs of register 18 are outputs 2 of the PLA. The first 23 and second 24 inputs of the control unit 16 16 are the control inputs 4 and 5 of the PLA. The third input 25 of the control unit 16 is connected to the input 3 of the PLC synchronization, which

five

50

) 5 5 0 ,,

also connected to the synchronization inputs of the registers 12-15 and 18. The fourth 26 and fifth 27 inputs of the control unit 16 are connected respectively to the outputs of the control units 8 and 9. The first output 28 of control unit 16 is connected to the control inputs of registers 13-15, the second output 29 is connected to the installation inputs of registers 13-15, and the third output 30 is connected to the address input of multiplexer 17 and to the control inputs of registers 12 and 18. Fourth output 31 of control unit 16 is the first additional output 7 of the PLA. The first information input of the multiplexer I7 is connected to the output of the higher bit of register 12, and the second information input is connected to the output of the lower bit of register 15 and connected, in addition, to the input of the sequential reception of information of the register 12 and to the second additional output 6 of the PLA. The output of the multiplexer 17 is connected to the input of sequential reception of register information 13, the output of the lower bit of register 13 is connected to the input of sequential reception of information of the register 14, and the output of the lower digit of register 14 is connected to the input of sequential reception of information of register 15.

In order to prevent races, registers 12-15 and 18 are executed in a two-step scheme or on a Z-latch type of DC-flip-flops with asynchronous setup inputs.

The operating mode of the PLA is determined by the corresponding set of signals at its inputs 4 and 5. The PLA can operate in the modes of input information conversion, accelerated self-checking and full checking.

To implement the necessary functions to convert the input information, the CTMs are pre-configured by selectively disconnecting or connecting the communication elements in the matrices 10 and 11 by any known method (for example, cutting or melting jumpers, destroying transitions, loading configuration information into memory elements). tew, etc.).

PLA works as follows.

In the input information conversion mode, the output 28 of the control unit 16 generates a signal prohibiting shifts and allowing parallel reception of information into registers 13-15. Output 30 sets a signal that prohibits shifts in register 12 and allows reception of information into register 18. The initial state of registers 12–15 and 18 can be arbitrary. At inputs 1, the CCPM is supplied with an n-bit input word to be converted into a k-bit output word. On the first clock pulse arriving at input 3 of the PLA, the input word is received in registers 13 and 14, whereby register 13 is entered directly, and register 14 is the inverse of all bits of this word. From the inverse outputs of the register 13, the inverse values of the bits of the received word are supplied to the inputs 194-19 of the matrix 10, and the inverse outputs 19p +. - 19 of the register 14 are the direct values of the bits of the same word. In accordance with the setting of the matrix 10, at the outputs 20, a t-bit intermediate word is formed. According to the second clock pulse, this word is entered into registers 12 and 15. From the outputs of register 15, the intermediate word is fed to the inputs 21 of matrix 11. According to the setting of matrix 11, the t-bit intermediate word is transformed into a k-bit output word, which is transmitted from the outputs 22 of the matrix 11 to the inputs of the register 18. On the third clock pulse, the output k-bit word is received into the register 18 and outputted to the information outputs 2 of the PLM. Each output slave corresponding to the input word received at input 1, - 1 "PLA in the rth cycle, appears at outputs 2 of the PLA in (p + 2) --th time ... In any rm. In the tact, the matrix U transforms the pth input word into the pth intermediate word, with matrix 11 it converts the (pl) -ro intermediate word into (p-1) -th output word, and register 18 stores (p-2) th output word. Thus, the transformation of the input information into the PLM is performed according to the principle of pipelining of words.

The accelerated self-test mode can be used to determine the health of the CMM directly at the site of its application for the main purpose (for example, in systems with temporary or hardware redundancy). Switch to Self

O 5 0 5 0 5 0 -5

0

The checks from the input information conversion mode are performed by a corresponding change of signals at the control inputs 4 and 5 of the PLA. As a result of this change, a single pulse appears at the output 29 of the control unit 16, setting one of the bits of the registers 13-15 (for example, the most significant bit of the register 13) to a single state, and the remaining bits to a zero state. At the output 28 of the control unit 16, an accelerated self-test is set at all times. A signal is set up that permits shifts and prohibits parallel reception of information into registers 13-15. At the output 30 of the control unit 16, a signal is generated, inhibiting shifts in register 12 and allowing reception of information into register 18 and the transmission of information pushed out during shifts from register 15 through multiplexer 17 into register 13. As a result, a ring shift register is formed. The latter of the serially connected registers 13-15. For each clock pulse from the input 3 PLA in the formed ring register. there is a cyclic shift unit. for one bit. When advancing a unit through registers 13 and 14, the inputs are sequentially polled, i.e. horizontal widths, matrices -10. From the inverse outputs of registers 13 and 14 and the i-th polled bus matrix 10 receives a zero signal, and the remaining tires - single signals. As a result of polling the i-input of the matrix 10 at its outputs 20, the i-e intermediate word appears, consisting of the main and check bits. As in the prototype, part of the columns of matrix 10 (e.g., one m-th column) is used to form the check bits. The content of the check bits in each intermediate word is determined by the contents of the main bits of this word and the type of control used. So, using parity, the number of connected elements during adjustment of the communication elements in each i-th row of the matrix 10 can be added to even, In this case, each intermediate word appearing during polling, at outputs 20 of matrix 10, must contain an even number of zeros. The formed intermediate word enters the control unit 8.

If there is no error, then no-error signals are set at the output of the control unit 8 and at the output 31 of the control unit 16. The signals at the outputs 28-30 of the control unit 16 do not change. At the next sync pulse i-e, the intermediate word is received from the outputs 20 of the matrix 10 to the register 12, and the contents of the registers 13-15 are cyclically shifted by one bit. In the next cycle, the (i + l) -ro input of the matrix 10 is polled, and so on. The self-test of the matrix 10 takes 2 steps.

From the beginning (2p-I) of the cycle, the unit is transferred from the low-order bit of register 14 to the high-order bit of register 15. Next, a self-test of matrix 1 I I is performed according to the principle described for matrix 10.

As the unit advances through register 15, the inputs are sequentially polled, i.e. vertical busbars, matrices 11. In each j-th cycle (j I, m) from the direct outputs of register 15 to the j-th input of the matrices. 11 a single signal arrives, and the remaining inputs are zero signals. As a result of the interrogation of the j-ro of the input of the matrix 11 at its outputs 22, an output word appears, which, like the intermediate words, consists of the main and check bits. This word enters the control unit 9, in which it is checked for correctness.

units and perceived by block 8 control as correct.

If in the current tact of accelerated self-check by any of blocks 8 and 9

5, if an incorrect word arriving at its inputs is detected, a signal appears at the output of this block, an error, which is transmitted to the corresponding input 25 or

 About 26 control unit 16. At the output 31 of the control unit 16, i.e. At the first additional output 7 PML, a malfunction signal is generated, indicating the detection of defects

 5 in OR.

The accelerated self-test cycle takes 2n + m cycles. From the beginning of the (2p + + m + 1) -th cycle, unit transfer is performed; from the low-order bit of register 15 through multiplexer 57 to the high bit of register 13. Next, the cycle of the accelerated self-test of the PLA is repeated until it is changed by the set of signals at the control inputs 4 and 5 of the PLA. The performance of a self-reversed PLA is indicated by the absence of malfunction signals at its output 7.

The refined self-test mode can be used to locate defects quickly in order to eliminate them or circumvent them by reconfiguring the PLA. The difference between the work of CTM in the mode of the refined self-test from

20

25

X

If there is no error, then the output of the unit in the accelerated self-test mode 9 of the control and the output 31 of the control unit 16 are set to no-error signals. The signals at the outputs 28-30 of the control unit 16 do not change. At the next sync pulse, the jth output word is received from the outputs 22 of matrix 11 to register 18, and the contents of registers 13-15 are cyclically shifted by one bit. A poll is performed at the next clock (j O ro input of matrix II, etc.

In the process of polling the inputs of the matrix 10 on all inputs of the matrix 11 there are zero signals. At the same time, at the outputs 22 of the matrix 11, the output word consisting of all zeros must be kept and perceived by the control unit 9 as correct. In the process of polling the inputs of the matrix 11 on all the inputs 19 of the matrix 10 there are single signals. at outputs 20 of matrix 10, an intermediate word consisting of one

units and perceived by block 8 controls as correct.

If in the current tact of accelerated self-check by any of blocks 8 and 9

if an incorrect word arriving at its inputs is detected, a signal appears at the output of this block, an error, which is transmitted to the corresponding input 25 or

26 control block 16. At the output 31 of the control unit 16, i.e. At the first additional output 7 PML, a malfunction signal is generated, indicating the detection of defects

in the OR.

The accelerated self-test cycle takes 2n + m cycles. From the beginning of the (2p + + m + 1) -th cycle, unit transfer is performed; from the low-order bit of register 15 through multiplexer 57 to the high-order bit of register 13. Next, the cycle of the accelerated self-test of the PLA is repeated until the set of signals at the control inputs 4 and 5 of the PLA is changed. The absence of malfunction signals at its output 7 indicates the health of the self-verifiable PLM.

The refined self-test mode can be used by the DP to quickly search for defects with a view to their subsequent elimination or circumvention by reconfiguring the PLA. The difference between the work of CTM in the mode of the refined self-test from

Verka is as follows.

If in the current cycle of a refined self-check, any of blocks 8 and 9 of the control detects an inaccuracy of a word arriving at its inputs, then an error signal appears at the output of this control block and a signal at the output 31 of control block 16

malfunction. On the next sync pulse, the contents of the registers 13-15 are cyclically shifted by one bit. Thereby, the next input of the matrix 10 or

11. At the same time, intermediate word is output from outputs 20 of matrix 10 to register 12 and output words from outputs 22 of matrix 11 to register 18. At output 30 of control block 16

an interrupt signal appears. This signal prevents parallel reception of information into register 12, offsets in register 12 are permitted, and the transfer of information by a serial code from

register 12 through multiplexer 17 to register 13. The same signal prohibits the reception of information into register 18 and the transfer of information from register 15 through multiplexer 17 to register 13. As a result, a ring shift register consisting of serially connected registers 12-15 is formed. the next sync pulse is cyclically shifted to the information in registers 12-15. As it shifts, this information is provided by a serial code from register 15 to output 6 of the PLA. The interrupt signal is held at the output 30 of the control unit 16 for 2 (n + m) cycles. For a specified period of time, 2 (n + t) -signal word is output to the exit of the 6 GSM. The first t + 2p bits of this word contain information cyclically shifted by one bit about the signals that occurred in. the moment of error detection at inputs 21 of matrix 1 1 and at inputs 19 of matrix 10, and the last m bits is an intermediate word that occurred at the same time at outputs 20 of matrix 10. Output word that occurred at the time of detection of an error at outputs 22 matrix 11 is stored in register 18.

Thus, for 2 (n + m) interrupt cycles at outputs 7 and 2 of the PLA, diagnostic information is obtained on the state of all inputs and all outputs of elements AND of matrix 10 and elements of OR matrix 11. Analysis of this information allows you to localize any settings defects, detected by blocks 8 and 9 of the control, up to individual elements of the matrix 10 and 11. Indeed, the presence of defects such as an extra element of the communication in the i-th row of the matrix 10 results in polling this line to the appearance of extra zeros in the corresponding bits i -ro intermediate word. The presence of defects such as the missing link element in the i-th row of the matrix 10 is accompanied by polling this row with the appearance of extra units in the corresponding i-ro bits of the intermediate word. Similarly, the lack or excess of communication elements in the jth column of matrix 11 leads to the appearance of extra zeros or ones in the jth output word, respectively. Knowing how the row of the matrix 10 (column of the matrix 11) was surveyed, and comparing the half5

004568

Interrupt (output) word with a reference word as a result of interruption, it is possible to establish where exactly which defects occur in PLM.LO-5. Calibration of detected defects of the system with accuracy to individual communication elements makes it possible to restore the working capacity of the PLM by eliminating or bypassing defects by a corresponding reconfiguration of the matrices 10 and 1 I.

After issuing diagnostic information, i.e. after 2 (p + m) cyclic shift cycles, the contents of each of the registers 12–15 are automatically restored (becomes the same IMI as it was at the time of the interrupt signal output by the control unit 16). Exit 30

 control block 16, instead of an interrupt signal, sets a signal that prohibits shifts in register 12 and enables parallel reception in registers 12 and 18 and the transmission of information by a serial code from a register

15 through multiplexer 17 into register 13. Thus, the interrupted point is returned to the continuation of the sequential interrogation of the inputs of matrices 10 and 11. The PLA operates in the refined self-test mode repeatedly repeated as described above until the set of signals on its controllers is changed. entrances

5 4 and 5.

The full check mode of the PLA is focused on the case when the reliability of the detection of defects must be particularly high. It can be used, for example, in organizing an output control for a PLA intended for use as part of non-recoverable computing devices.

 V.- mode of full check PLM block

The 16 control produces a periodic change of signals at its output 30, regardless of the signals coming from blocks 8 and 9 of the control. For one clock cycle, at the output 30 of block 16, the signal is held enabling the interrogation of matrices 10 and 11, and for the next 2 (n + m ) cycles - interrupt signal, which provides the diagnostic information obtained from the PLA, which was obtained when polling.

The complete PLM check cycle includes 2n + m polling cycles and 2 (n + m) (2n + m)

0

91300456 About

cycles of issuing diagnostic information received in polling cycles. With this sequence

sa to the inputs 19 of matrix 10, has vic

SP .. .11,101 ... 11,110 ... 11, ..., PC .. 10,111 ... II, 111 ... 11

--- ,,,,

2n impacts

and represents, for each of the elements of AND of the matrix 10, a complete verification test that can detect any constant defects of these elements ... 00 ... 00, ..., 000 ... 00,100 ... 00,010.,. 00,001 ... 00 , ..., 000 ... 01

2n impact

and represents, for each of the ed 4ents of OR of matrix 11, a complete testing test that can detect any constant defects of these elements. Consequently, the means introduced into the PLM provide for the generation of complete verification tests for cells of matrices 10 and 11, the execution of tests, as well as the issuance of the results of the execution of tests for outputs 6 and 2 of PLA. The issuance of test results from the PLM makes it possible to detect any constant defects of matrices 10 and 11, including those defects that are not detected by blocks 8 and 9 of the control.

The complete PLM check cycles are repeated several times until the set of signals at its control inputs 4 and 5 is changed.

Claims (1)

Invention Formula A programmable logic matrix containing AND elements, OR elements, two control blocks, the inputs of which are connected to the outputs of the AND elements and the SHS elements, respectively, the first buffer shift register, the synchronization input of which is the synchronization input of the programmable logic matrix, that, in order to increase the reliability of the programmable logic matrix, the first and second input, output and second buffer shift registers, the multiplexer and the control unit are introduced, and the parallel reception inputs and the information of the first and second input registers are the information inputs of the programmable logic array, and the output is connected respectively to the inputs / impacts coming in ticks sa to the inputs 19 of matrix 10, has vic cops. Similarly, the sequence of actions in the polling cycles at the inputs 21 of the matrix i1 is 0 25 jq 35 Q d m impacts And elements, the inputs of the parallel reception of information of the first and second buffer shift registers are connected to the outputs of the AND elements, and the outputs of the second buffer register of the shift are connected to the inputs of the OR elements, the outputs of which are connected to the inputs of the parallel reception of information of the output shift register, whose outputs are information outputs programmable logic matrix, sequential information outputs of the first buffer and first and second input shift registers are connected respectively to the first information A multiplexer input, with a serial information input of the second input shift register and a serial information input of the second buffer shift register, the serial information output connected to the serial information input of the first buffer register, and the second information input of the programmable logic matrix, the multiplexer output is connected to the serial information input of the first input register and the shift, the first and second inputs of the control unit are respectively the first and second inputs of the programmable logic array operation mode, the third input of the control unit is connected to the synchronization inputs of all shift registers, the fourth and p1 inputs of the control unit are connected to the outputs of the first and second control units , the first and second outputs of the control unit are connected respectively to the control and installation inputs of the first and second input and П130045612 the second buffer registers and the output shift registers, and the chet-shift, the third output from the controlled output is the control sensing inputs. multiplexing of the programmable logic mat, the first buffer layer.