SU1292164A1 - Multichannel pulse sequence generator - Google Patents

Abstract

The invention relates to a pulse technique and can be used in devices for generating periodic sequences of pulses that control microcircuits with charge coupling. The aim of the invention is to increase the speed and reliability by reducing the capacity of the memory blocks. The device contains a generator of I clock pulses, a counter of 7 addresses with a counting input 8, a start input 9 and outputs of bits 10-13, a memory block 14 with an output I5. In order to achieve this goal, a shaper of the formation of periodic phase pulse sequences with input 3 and outputs 4-6, a memory block 16 with input 17 of recording and outputs 18-20 are entered into the shaper, new connections are formed. An example of a specific implementation of block 2 is proposed. 2 c.p. f-ly, 2 ill. from € (L b

Description

The invention relates to a pulse technique and can be used in devices for generating periodic sequences of pulses that control microcircuits with charge coupling.

The purpose of the invention is to increase speed and increase reliability by reducing the capacity of the memory blocks.

Figure 1 shows the functional diagram of the multichannel pulse trainer; Fig. 2 is a functional diagram of a unit for generating periodic phase sequences of pulses (an example of a specific implementation).

The device contains a generator of 1 clock pulses, a block 2 forming periodic phase pulse sequences with input 3 and outputs 4-6, a counter 7 addresses with a counting input 8, start input 9 (input bus) and outputs 10-13 bits, memory block 14 with output 15, block 16 of RAM with input 17 of the record and outputs 18-20.

The output of the generator 1 is connected to the input 3 of the unit 2, the outputs 4-6 of which are connected to the input data buses of the RAM 16. Input input 9 is connected to the start input of the 7 address counter, counting

fO

f5

20

25

thirty

elements And 24-26, the second inputs of which are connected to the outputs of the corresponding D-flip-flops 27-29. The outputs of the elements 24-26 are connected to the corresponding outputs 4-6 of block 2.

Block 2 of the formation of periodic phase sequences (figure 2) contains the element EXCLUSIVE OR 30, the shift register 31 with the input 32 synchronization, elements And 33-35, the shift register 36 with the input 37 synchronization, the element EXCLUSIVE OR 38, the inverter 39.

The outputs of the two bits of the shift register 31 through the element EXCLUSIVE OR 38 are connected to its input sequential data recording. The outputs of the two bits of the shift register 36 through the element ISKShKOYUY and ITS R1PI 30 connected to its input sequential data recording. The first inputs of elements AND 33-35 are connected to the outputs of the shift register 31, and the second inputs are connected to the outputs of the bits of the shift register 36. The outputs of elements AND 33-35 are outputs 4-6 of block 2. Synchronization input 32 is direct, and input 37 synchronization via inverter 39 is connected to the input 3 of block 2.

The device works as follows.

35

The pulse sequence with a period T from the output of the generator 1 is fed to the input 3 of the block 2. The negative differential voltage at the synchronization input 23 of the shift register 22 shifts the information on the ram memory, the outputs 18-20 of which are O ° bit and written to the first bits are device outputs. the shift register 22 is zero or one from the output of the element ISKLOCHAKEYE Block 2 of the formation of periodic phase sequences pulsed input 8 of which is connected to the output 4 of block 2. The outputs 10-13 of the bits of the counter 7 addresses are connected to the corresponding address inputs of memory block 14, output 15 of which is connected to the input 17 of the recording block 16 opeza output element Sh1I 21, using D-flip-flops 27-29 and logic elements And 24-26

owls (figure 1). contains the element EXCLUSIVE-45 provides for the overlapping of phase IMTsEE OR 21, the shift register 22 from the pulses at the outputs 4-6 for the duration of the synchronization input 23, logic gates And 24-26, D-triggers 27-29. The clock inputs of the D-flip-flops 27-29 are combined and connected to the input, 23 sync jfj, with the 9th start of the logical zero counting of the shift register 22 and the input 3 of the block 2. The first and the second outputs of the shift register register 22 through the element EATING OR 21 drowsiness pulse t, arriving at the input 23 of the synchronization of the shift register. 22. With the arrival on the input chichik 7 addresses gets permission to count the number of input pulses. At the counting input 8 of the address counter 7, a count is made of the pulsed numbers with its input of a serial 5 co of one of the phases, for example, the first one from the data record. The outputs of the bits of the shift output 4, entering the input bus- 22

gob register 22 is connected to the information inputs of the corresponding D-flip-flops 27-29 and the first inputs

data block 16 RAM. Memory block 14 is programmed in such a way that by addresses less

five

0

five

0

elements And 24-26, the second inputs of which are connected to the outputs of the corresponding D-flip-flops 27-29. The outputs of the elements 24-26 are connected to the corresponding outputs 4-6 of block 2.

Block 2 of the formation of periodic phase sequences (figure 2) contains the element EXCLUSIVE OR 30, the shift register 31 with the input 32 synchronization, elements And 33-35, the shift register 36 with the input 37 synchronization, the element EXCLUSIVE OR 38, the inverter 39.

The outputs of the two bits of the shift register 31 through the element EXCLUSIVE OR 38 are connected to its input sequential data recording. The outputs of the two bits of the shift register 36 through the element ISKShKOYUY and ITS R1PI 30 connected to its input sequential data recording. The first inputs of elements AND 33-35 are connected to the outputs of the shift register 31, and the second inputs are connected to the outputs of the bits of the shift register 36. The outputs of elements AND 33-35 are outputs 4-6 of block 2. Synchronization input 32 is direct, and input 37 synchronization via inverter 39 is connected to the input 3 of block 2.

The device works as follows.

The pulse sequence with a period T from the output of the generator 1 is fed to the input 3 of block 2. By a negative voltage drop to the synchronization input 23 of the shift register 22, information is shifted by ° bit and the first bit of the shift register is 22 zero or one unit Element Outlet INSULATE

from the output of the element Ш1И 21, with the help of D-flip-flops 27-29 and logic elements AND 24-26

the overlapping of phase pulses at the outputs 4-6 for the duration of the 9 start of the logical zero counting is provided

the impulse t received at the synchronization input 23 of the shift register. 22. With the arrival of the input, the overlapping of the phase pulses at the outputs 4-6 for the duration of the 9th run of the logical zero of the

Chick 7 addresses gets permission to count the number of input pulses. The counting input 8 of the address counter 7 is used to count the number of pulses from one of the phases, for example, the first from output 4, arriving at the input terminals

data block 16 RAM. Memory block 14 is programmed in such a way that by the addresses of les31

W S in memory block 1A, units recorded from the input 15 of memory 14 to input 17 of the recording of memory 16, which operates in the pass-through mode of pulses from the input data bus to outputs 18-20, are recorded. Upon reaching the address corresponding to the value S, the output 15 of the memory block 1A appears zero, with the help of which the information stored on the input data bus of the RAM 16 at this moment in time is written to the RAM 16 and the passage of data from the inputs to the outputs 18-20 of the RAM 16 (FIG. 2).

The operation of the device with block 2 in figure 2 is similar to that described and it works as follows.

But to a negative voltage drop at the input 32 of the synchronization of the shift register 31, information is shifted in the shift register 31 by one bit and written to its first bit zero or one from the output of the EXCLUSIVE OR 38 element.

The clock pulses from the output of the generator 1 in inverted form through the inverter 39 are fed to the synchronization register 36 input to the shift register 36, while the pulses at its outputs are shifted relative to the pulses at the outputs of the shift register 31 by the pulse duration t of the generator 1. -35 ensures the formation of the overlap of the output phase pulses of block 2, arriving at the outputs 18-20 of the device, for the duration of the pulse of the generator of 1 clock pulses.

Claims (3)

Invention Formula . A multichannel pulse sequence shaper containing a clock pulse generator, an address counter, whose bit outputs are connected to the corresponding address inputs of a memory block, characterized in that, in order to improve speed and increase reliability, a pulse phase formation sequence is introduced into it Ш 15 20 25 30 35 0 five 0 5 644. and an operating memory, the output of the clock generator is connected to the input of a unit for generating periodic phase sequences of pulses, the outputs of which are connected to the corresponding input data buses of the operating memory unit, the counting input of the address counter is connected to the first output of a unit for generating periodic phase sequences of pulses, and the output of the memory unit is connected to the write input of the main memory unit, the launch input of the address counter is connected to the start value. 2. The multi-driver shaper of claim 1, characterized in that the block for generating periodic phase sequences of pulses contains a shift register, the outputs of which bits are connected with the information inputs of the corresponding D-flip-flops and the first inputs of the corresponding elements And, the second inputs of which are connected to the outputs of the corresponding D-flip-flops, the input of the block is connected to the synchronization input of the shift register and the combined clock inputs of the D-triggers through the EXCLUSIVE element OR is connected to its serial data input; the outputs of the AND elements are the outputs of the block. 3. The multi-channel driver according to claim 1, characterized in that the unit for generating periodic phase sequences of pulses comprises a first shift register, the outputs of which are connected to the first inputs of the elements AND, a second shift register whose outputs are connected to the second inputs of the elements of I, the first and second outputs bits of each shift register through the elements of ICCP10CHA1 ALTERNE OR are connected to their inputs of sequential data recording, the input of the block is connected to the synchronization input of the first shift register directly enno and to the input of the second synchronization shift register via an inverter, elements and outputs are the outputs. . Editor S.Pekar Compiled by Yu.Sibir to Tehred V. KadarKorrektor G. Reshetnik Order 285/57 Circulation 902. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk iab., d. 4/5 Production and printing company, Uzhgorod, Projecto st., 4 (pua2.