SU1292040A1 - Device for checking internal memory - Google Patents

Abstract

The invention relates to computing and can be used for test monitoring of LSI memory and random access memory (RAM) devices. The aim of the invention is to increase the speed of the device. The device contains the first, second, and third address counters, ring shift registers, and a comparison unit. The speed of the device is achieved by forming test effects of a ring with a p: dpigram each time the device is synchronized. 1 il. ISD p N3

Description

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The invention relates to computing and can be used for test monitoring of LSI memory and random access memory (RAM) devices.

The aim of the invention is to improve the speed of the device.

The drawing shows a diagram of a device for monitoring RAM blocks.

The device contains a comparison unit 1, the third counter 2, whose outputs 3 are the device’s address outputs, one input connected to the output of the first group of ring offsets 4, inputs 5, 6, 8 and 9 are connected to the outputs of the first and second counters 10 and 11, and the other inputs 7 are the device inputs, the outputs 12 of the second shift group ring registers 13, and the outputs 14 of the third group ring shift registers 15. The drawing also shows the information inputs 16 of the device, the controlled RAM 17, the synchronization input 18 and the error output 19.

The RAM is monitored according to tests, in which certain sequences (cycles) of RAM calls are repeated several times. For example, in a checkerboard test, the sequences of writing O and 1 are repeated, and then read them. For other tests, more complex cycles are possible.

Information about the first cycle of calls to RAM 17 is recorded in registers 4, 13, 15, and the initial address of the control is recorded in counter 2. This information 0 represents sequences of logical states that need to be set at the corresponding inputs of RAM 17 and counter 2 so that the test provided for 5 test sequence of calls to the RAM 17 within the cycle. What logical states need to be set at the inputs of RAM 17 to

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made a call to him, providing for the command account forwards, counting back, zarenno test, are known from the description of the principle of operation of a particular controlled RAM 17, and logical conditions that need to be set on the inputs of counter 2, in order for the address change to occur, are known from description of the principle of operation of the specific counter 2.

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Thus, the information needed to write to the elements 2, 4, 13, 15 is known from the description of the operating principle of the specific RAM and counter 2 and the description (algorithm) of the selected control test.

The registers 4 controlling the operation of counter 2 are needed only if the cycle of calls to RAM 17 provides not only the counting of counter 2 forwards, but also its other operations, such as counting back or recording information from parallel inputs 5, or 6, or 8, or 9. The signals from these registers, and implement the corresponding control of the counter 2.

If the specified cycle of calls to the RAM. includes abrupt jumps of addresses, for example, returning an address to several memory cells backwards or forwards (for example, the Additional Addressing test), you can use counters of type 10 and 11 connected to the parallel inputs of counter 2, to which information is also pre-recorded. In the process of operation of the device, the counting in these counters takes place and the information is copied from their outputs into counter 2, which is controlled. signals from registers 4.

Information into the elements 2, 4, 10, 11, -13, 15 is recorded in parallel (i.e., almost simultaneously) through their inputs D 7 from parallel registers, in particular the output ports of the control computer, for example, Electra, nickname K1-20. Do this by any means known.

After recording the information in the elements 2, 4, 10, 11, 13, 15, clock pulses are fed to the bus 18. On the leading edge of the clock pulse, information is shifted in registers 4 and the counter in counters 10 and 11, the counter runs on its trailing edge 2 commands, the code of which is installed on its control inputs, i.e. at the outputs of registers 4, for example.

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0

writing from parallel inputs 5, or 6, or 8, or 9. On the falling edge of a clock pulse, information is shifted in registers 13 and 15. At inputs 12 of RAM 17, the information to be written to RAM 17 or expected to be read from RAM 17. At the control inputs 14 of RAM 17, a write command code in RAM is set.

17 or read from RAM 17 or regeneration, etc. depending on the content of the cycle. If there is a need for a strobe signal in RAM 17 (the signal on which RAM 17 executes 5 commands, the signal bus is not shown conventionally in the diagram), it can be supplied to RAM 17 after shifting the information in registers 15. If inputs 14 have the formula of the invention

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before the next recording of information in the specified elements. With long intervals of time between two recordings of information in the indicated elements, it is possible to have time to prepare information, for several subsequent recordings, -. so that, at short intervals between two recordings of information in the indicated elements, be reduced to

the read command code is forced, the minimum delay fO of the device, the output of the outputs 16, appears to be a role-read information preparation.

with RAM 17 information which is block 1

compared with the expected information

set at this time on the outputs

registers 13. In case of malfunctioning RAM

17 an incomparable signal appears

output 19 of block 1. At this time

Inputs 3 RAM 17 is present address

the memory cells with which it happened

reading incorrect information.

Clock feed to bus 18

carried out as long as agreed

but the test is carried out the same cycles of accessing the RAM 17. During this time in registers 4, 13,

15 info {maci circulating around the ring

(i.e., serial to

serial input). Once

at the inputs 3 RAM 17 is installed

address after which according to the test

other cycles needed

calls to RAM 17 (for example, in the simplest case, after cycles of records

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An operative memory control device comprising a comparison unit, the inputs of the first group of which are information inputs of the device, the first and second counters, characterized in that, in order to improve speed, a third counter and ring shift registers are inserted, and the installation inputs are ring the shift registers, the first and second counters, and the installation inputs of the first group of the third counter are the installation inputs of the device, the control inputs of the third counter are connected to the outputs of the ring pe ISTRY shifting the first group and second inputs .ustanovochnye TpeTbeii groups of the third counter are connected respectively to the outputs of the first and

O, it is necessary to write 1 or read), write to the elements 4, 10, 11, 13, 15 other information — about new cycles of accessing RAM 17. Then again, clock pulses are sent to bus 18, making calls to RAM 17. And so on until the RAM control test is completed.

To save time, it is possible immediately after recording the information in elements 4, 10, 11, 13, 15 to start preparing information on the next cycles of accessing RAM 17 in computer ports and have time to prepare it

Claims (1)

Invention Formula An operative memory control device comprising a comparison unit, the inputs of the first group of which are information inputs of the device, the first and second counters, characterized in that, in order to improve speed, a third counter and ring shift registers are inserted, and the installation inputs are ring the shift registers, the first and second counters, and the installation inputs of the first group of the third counter are the installation inputs of the device, the control inputs of the third counter are connected to the outputs of the ring pe ISTRY shifting the first group and second inputs .ustanovochnye TpeTbeii groups of the third counter are connected respectively to the outputs of the first and The second counters, and the outputs are the device's output addresses, the inputs of the second group of the comparison unit are connected to the outputs of the ring shift registers of the second group and are information outputs of the device, the output of the comparison unit and the outputs of the ring shift registers of the third group are respectively the error output and control the device outputs, the three-way inputs of the first, second, third counters, and ring shift registers are combined and are the device sync input. Editor A.Vorovich Compiled by O. Isaev Tehred A. Kravchuk Order 277 / 5t Circulation 590 Subscription VINILI State Committee of the USSR for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 Proofreader G. Reshetnik