SU1287263A1 - Current pulse conditioner - Google Patents

Abstract

The invention can be used to control various devices with an inductive load pattern. The purpose of the invention is povighenie stability of the amplitude of the output pulses. The driver contains an electronic switch 1, inductive load 2, feedback element 3, damping element 4 and comparator 5. Introduction of a threshold formation unit 6, a driver unit 7, a control unit 8, the formation of new functional connections and the proposed constructive implementation of the threshold formation unit 6 , the control unit 8, the initial setting pulse generator and the delayed pulse former contribute to the achievement of the set goal. 4 hp f-ly, 8 ill. with S (L

Description

1128

The invention relates to a pulse technique and can be used to control various devices with the inductive nature of the load, for example, waveguide switches.

The purpose of the invention is to increase the stability of the amplitude of the output pulses.

FIG. 1 shows a structural electrical circuit of the device; in fig. 2 - time diagrams of the device; in fig. 3 is a structural electrical circuit of a threshold formation unit; Fig. 4 is a structural electrical circuit of the control unit; in fig. 5 is a structural electrical circuit of the pulse setter of the initial installation; Fig. 6 shows voltage diagrams for the operation of a pulse shaper of the initial installation; in fig. 7 is a structural electrical circuit of the first delayed pulse former; in fig. 8 - voltage plots for the operation of the first delayed pulse shaper.

Current pulse shaper contains electronic key 1; induk

tivnuyu load 2, element 3 reverse pulses 30, the output element And 15

3

2

The threshold shaping unit 6 contains a peak detector 9, a comparator 10, a first digital-to-analog converter (ILP) I, a first driver I 2 delayed 11 pulses, a first element OR 13, an RS flip-flop 1A, element 15, a generator 16 clock pulses, counters 17 and 18, pulses, the second shaper 19 of the delayed pulses, the first adder 20, the multiplexer 21, the second adder 22, the register 23, the second DAC 24, the shaper 25 of the initial setup pulses and the second element SHSh 26.

The information input of the peak detector 9 is the analog input of the threshold formation unit 6, the output of the peak detector 9 is connected to the first input of the comparator 10, the second input of which is connected to the output of the first NAL 11, the output of the comparator 10 is connected to the input of the OR 13 element , the output of which is connected to the R-input of the RS flip-flop 14, the output of which is connected to the first input of the element 15, the second input of which is connected to the output of the clock generator 16

connection, a damping element 4, a comparator 5, a formation unit 6, a threshold, a driver unit 7, and a control unit 8.

The first input of the electronic key 1 is connected by a power source, and in: i- a turn with the first output of the damping element 4 and the first output of the inductive load 2, the second output of which is connected to the input of the feedback element 3, the first output of which is connected to the first input of the comparator 5 and the analog input of the threshold formation unit 6, and the second output

and the second output of the damping element 45, the second group of discharge

This 4 is connected to a common length, the second input of the comparator 5 is connected to the information output of the threshold generation unit 6, the digital input of which is connected to the output of the master unit 7, while the output of the comparator 5 is connected to the first input of the control unit 8, the second input of which is connected

the inputs of which are connected to the first group of bit inputs of the multiplexer 21 and is the input 6 of threshold formation, the bits 50 of the outputs of the adder 20 are connected to the group of bits of the inputs of the summer 22, the second group of bits of the inputs of which are connected to the different outputs of the register 23, razr

with the installation output of the threshold formation unit 6, and the third input — with and 55 — the outputs of the adder 22 are connected to the control input of the block 6 by forming the second group of discharge inputs of the threshold and the input thickness of the device, and the output from the control input of the electronic key.

multiplexer 21, the bit of which you are connected to the discharge formation inputs of the register

connected to the subtracting input of the counter 1 7 pulses and the summing input of the counter 18 pulses, the discharge outputs of which are connected to the input

35 of the first digital-to-analog converter 11, the inputs for setting the zeroing of the counters 17 and 18 pulses are connected to the input of the driver 19 and are controllable by the input of the block 6

40 of the threshold formation, the output of the imaging unit 19 is connected to the S input of the RS flip-flop 14, the discharge outputs of the pulse counter 17 are connected to the first group of discharge inputs of the summation inputs of which are connected to the first group of discharge inputs of the multiplexer 21 and are the input of the threshold formation unit the bit 50 outputs of the adder 20 are connected to the first group of bit inputs of the adder 22, the second group of bit inputs of which is connected to the bit bits of the register 23, the bits

55 outputs of the adder 22 are connected to the second group of bit inputs

the outputs of the adder 22 are connected to the second group of bit inputs

multiplexer 21, the bit outputs of which are connected to the bit information of the register 23

and the information inputs of the digital-to-analog converter 24, the output of which is the information output of the threshold generation unit, the first output of the driver 25 is connected to the control input of the multiplexer 21, the second input of the element OR 13 and the second output of the threshold formation unit 25 is connected to the first input element 26, the second input of which is connected to the control input of the peak detector 9 and the output of the imager 12, the output of the OR element 26 is connected to the synchronous input of the register 23 and the control input digital-to-analog converter 24,

The control unit 8 contains the element OR 27, the RS flip-flop 28 and the amplifier 29; the first and second inputs of the OR element 27 are respectively the first and second inputs of the control unit, the output of the OR element 27 is connected to the R input of the RS flip-flop 28, the S input of which is the third input of the control unit, the output of the trigger 28 is connected to the amplifier input 29, the output of which is the output of the control unit.

An initial setup pulse shaper contains: a series-connected formation element 30, a delay element 31, a NOT element 32 and an AND element, the second input of which is connected to the input of the element 31

The first delayed pulse shaper comprises a series-connected formation element 34, a delay element 35 and an AND element 36, the second input of which is connected to the input of the delay element 35. .

The device works as follows.

When power is applied, shaper 25 produces pulses in the first and second outputs in accordance with FIG. 6. The impulse and, from the first output of the imaging unit 25 is fed to the second input of the control unit 8, where it sets the trigger output 28 to O. This signal, amplified by the amplifier 29, is fed to the control input of the key 1, keeping it in the locked state. In addition, the impulse U enters through the element OR 13 at the R-input of RS-Tp irrepa 14 and sets it to O. Thus, at one of the inputs of the element 15, it is set

87263

ABOUT

same

ten

15

20

and, respectively, at the output of so-0. Pulses from the generator output 16 clock pulses do not arrive at the inputs of counters 17 and 18 pulses. In addition, the pulse U is fed to the control input of multiplexer 21 and connects its bit outputs to the first group of bit inputs, sets a binary code at its output coming from master block 7 and equal to the digital value of the specified pulse amplitude. A pulse U, j appearing with a delay at the second output of the generator -25 arrives at the synchronous input of the register 23 and the control input of the DAC 24 and writes this binary code into the memory of the register and the DAC, at the output of the DSC 24 and the second input of the comparator 5 sets the initial analog threshold value 1 to the specified value am5

0

five

0

pounds I

When the pulse is transferred to O and arrives at the control input of the multiplexer 21, the multiplexer output is connected to the second input of the multiplexer 21 connected to the output of the adder 22. The device is set to the initial state.

A start pulse, which arrives at the input of the device, arrives at the third input of the control unit 8 and sets the output of the trigger 28 to a state. The amplifier 29 amplifies this signal and supplies it to the control input of the electronic switch 1. The key 1 opens and an increasing current flows through the load 2 and the feedback element 3. Comparator 5 compares the value of the rising current with the initial threshold value 1 ,, and at the moment of equality it issues a pulse to the first input of block 8 and triggers trigger 28 to O. This signal by

5 is given to the control input of the electronic key 1. The key 1 is closed after the time t necessary for the absorption of the charge in the base of the transistor. At the moment of locking the key 1 on the load 2, a pulse of reverse polarity arises. At this moment, the damping element opens and dissipates the energy accumulated in load 2. Over time, the load continues to increase and an initial deviation of the pulse amplitude from the specified value (error) occurs. From the output: the feedback element 3, the pulse is fed to the peak input

51

the detector 9, and the detector remembers the amplitude of the pulse. The start pulse arrives at the device input, enters the installation inputs of the counters 17 and 18 pulses and zeroes them, and also starts the driver 19. The pulse from the driver output sets the output of the RS flip-flop 14

and I 11

state 1 and, therefore, sets the input element And 15 l. Therefore, the pulses from the generator output 16 clock pulses through the element 15 begin to flow to the corresponding inputs of the counters 17 and 18 pulses, and the counter 17 operates in the subtractive mode, and the counter 18 in the summing, From the output of the counter 18, the binary code enters the input Ts.P. 1, at the output of which a stepped rising voltage is generated, which is supplied to the second input of the comparator 10. At the time of equality of the stepped voltage and the output voltage of the peak detector 9 fed to the first input of the comparator 10, the output of the comparator a voltage difference occurs in 1 that enters the R-input of the RS flip-flop -14 through the element OR 13 and overturns the RS flip-flop 14 into O. At the output of the element 15, O is set and the counters I7 and 18 pulses stop counting. In addition, the voltage drop from the output of the comparator 10 is fed to the input of the driver 12.

Thus, at the outputs of the counters 17 and 18, the digital value of the amplitude of pulses 1 is set (at the output of the counter 18, in the forward code, and at the output of the counter 17, in the additional code BM). From the output of the counter 17, the digital value of the pulse amplitude in the additional code goes to the first input of the adder 20 and is summed with the digital value of the specified amplitude 1, and it arrives at the second input of the adder 20 in the forward code. At the output of the adder, the digital value of the error 5 appears in the forward or in the additional code. The digital value of the initial error S after the first current pulse in the load is obtained in the additional code, since in this case the amplitude of the pulse is greater than the specified value. The digital error value is fed to one input of the adder 22, to the other input of which the value of the previous threshold is received

tio

equal to the first one

amplitude value i. At the exit

5 (3 D

The adder 22 establishes a digital value of the new threshold, equal to the difference of the specified amplitude and error value. This value is fed to the second input of the multiplexer - 21. And is set at the output of the multiplexer, and hence at the information inputs of the register 23 and the DAC 24.

When a pulse occurs at the output of the driver 12, coming through the OR element 26 at the synchronous input of the register 23 and the control input of the DAC 24, this new threshold value is recorded in the memory of the DAC and the register. In addition, the pulse from the output of the imaging unit 12 is fed to the control input of the peak detector 9, where it is used to discharge the accumulative

condenser.

When the next trigger pulse arrives at the device input, counters 17 and 18 are again zeroed and the pulse edge is formed at the output of the comparator 10, the driver J9 is started, the trigger 28 is set to 1 and the formation of a new current pulse begins in the load. Comparator 5 now compares current to

load with a new threshold value of 1. At the time of comparison, a command is issued to turn off the key 1. At the time of locking the key, the diode of the damping element opens and retracts

energy stored in inductive load. The pulse amplitude is then measured, the primary error 8 is calculated (and the new threshold value is determined

-P1

which must be filed

to the second input of comparator 5 in order to minimize this error.

Measuring the error in each cycle and calculating the threshold value, the output of the threshold formation unit 6 is its value, which allows to receive current pulses in the load with a given amplitude with an accuracy of one least significant bit.

50

Claims (5)

Invention Formula I. A current pulse shaper containing an electronic switch, the first 55 input of which is connected to a power source, a feedback element, a damping element, a comparator and an inductive load, the first output of which is connected to the output of an electronic key and the first output of the damping element, and the second - with the input of the feedback element, the first output of which is connected to the first input of the comparator, and the second output of the feedback element and the second output of the damping element are connected to the RPM; In order to improve the stability of the amplitude of the output pulses, a threshold shaping unit, a control unit and a master unit are inserted in it, the first input of the comparator is connected to the analog input of the threshold shaping unit, the second input with information output b The threshold is formed, the digital input of which is connected to the output of the master unit, while the comparator output is connected to the first input of the control unit, the second input of which is connected to the installation output of the threshold shaping unit, and the third input to the control input of the device forming the threshold and the output is with the control input of the electronic key. 2. A device according to claim 1, characterized in that the threshold forming unit comprises a peak detector, two delayed pulse generators, a clock generator, a comparator, two OR elements, an AND element, an RS trigger, two digital-to-analog converters, two pulse counters , two adders, a multiplexer, a register and a pulse shaper of the initial setup, the peak detector information input being the analog input of the threshold shaping unit, the peak detector output connected to the first comparator input, the second input d which is connected to the output of the first digital-analog converter, the output to the input of the first delayed pulse generator and to the first input of the first OR element, the output of which is connected to the R input of the RS flip-flop, the output of which is connected to the first input of the AND element, the second input which is connected to the output of the clock pulse generator, the output with the subtracting input of the first pulse counter and the summing input of the second pulse counter, the outputs of which bits are connected to the inputs of the bits of the first digital-analog conversion Atel, installation inputs five 0 Zeroes of the first and second pulse counters are connected to the input of the second delayed pulse generator and are the control input of the threshold generation unit, the output of the second delayed pulse generator is connected to the S input of the trigger, and the discharge outputs of the first pulse counter are connected to the first group of discharge inputs of the first adder , the second groups of the bit inputs of which are connected to the first group of bit inputs of the multiplexer and are the digital input of the threshold generation unit, the bit outputs of the first an adder connected to the first bit group dny :: second adder inputs, a second set of bit inputs of which is connected to the discharge dnymi register outputs The discharge outlets of the second adder are connected to the second bit group of the multiplexer inputs, The discharge outlets are connected to data inputs 5 of the register and the second digital-analog converter, the output of which is the information output of the threshold generation unit, the first output of the initial setting pulse generator is connected to the control input of the multiplexer, the second input of the first OR element, and is the installation output of the threshold shaping unit, the second output of the initial pulse generator is connected to the first input of the second OR element, the second input of which is connected to the control input of the peak detector and the output of the first Q delayed pulse generator, output with a control input of the second and a synchronous input register. five 45 50 55 3. The device according to claim}, wherein the control unit comprises an amplifier, an RS flip-flop and an OR element, the amplifier output being the output of the control unit, the input is connected to the RS-trigger output, the R-input of the RS flip-flop is connected to output the OR element, the first and second inputs of which are, respectively, the first and second inputs of the control unit, the S input of the RS flip-flop is the third input of the control unit. J 4. The device according to claim 2, characterized in that the pulse shaper of the initial installation comprises a pulse shaper, an element, a delay, an inverter and an element, the output of the pulse shaper is connected to the input of the delay element and the first input of the element And, and the output of the delay element through an inverter is connected to the second input of the AND element and is the first output, and the output of the AND element is the second output of the initial setting pulse generator. tbiKit. . FIG. 2 5. The device according to claim 2, characterized in that the first delayed pulse shaper comprises a pulse shaper, a delay element and an element, and the input of the pulse shaper is an input bus, the output of which is connected to the first input of the And element and through the delay element with the second input whose output is the output of the first delayed pulse generator. D l tUKn. Un thirty FIG. five {pt / e. 31 t Sh 33 FIG. B fig 7 FIG. eight