SU1287229A1 - Buffer storage - Google Patents

Abstract

The invention relates to computing and can be used in the construction of high-speed buffer storage devices. The aim of the invention is to expand the field of application of the device by providing operation in random and sequential access modes. The device contains memory blocks I, counters-registers 2, adders 3, delay element 4, decoder 5, elements AND 6, single-oscillators 7. The device is provided with a mode of single calls at arbitrary addresses and a mode of successive calls with improved speed. 1 il.

Description

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The invention relates to computing and can be used in the construction of high-speed buffer storage devices.

The chain of the invention is to expand the scope of application by providing work in random and sequential access modes.

The drawing shows the scheme of the buffer storage device.

The device contains 1 memory blocks, counters-registers 2, adders 3 delay elements 4, decoder 5, elements AND 6, and one-shooters 7. In the same line, the inputs of the higher 8 and lower 9 bits of the device address, the installation inputs 10, the input references 11 and write / read 12, information outputs 13 and device inputs 14.

The device works as follows.

The main mode of operation of the device is the sequential access to the cells of memory 1 blods. The outputs of the counters-registers 2 are divided into a group of low-order bits (two bits for four memory blocks) and a group of high-order bits. The initial values in the group of high bits of all counters-registers 2 and in the group of low-order bits of one of the counters-registers 2 are recorded directly from address inputs 8 and 9 of the device. The contents of the faded bits groups are recorded from the outputs of the adders. 3, on the installation inputs 10 of which codes of numbers 3, 2 and 1 are formed.

Signals on input I1 increment the counters-registers 2, and the sequential start-up of cycles of memory 1 blocks occurs on signals from the decoder 5, which, having passed the corresponding elements of AND 6, start single-oscillators 7, which in turn generate signals of addressing the blocks 1 memory.

The introduction of adders 3 allows you to simultaneously form the address of the

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The introduction of one-shot 7 allows you to start accessing the next memory block, without waiting for the end of the previous one.

Claims (1)

Formula invented and Buffer storage device, containing memory blocks, information INPUTS and outputs of which are: respectively informational inputs and outputs of the device, and address inputs are connected to the high-level outputs of the corresponding counter-registers, the elements AND, O TL and so on that, in order to expand the scope of application due to the provision of operation in random and sequential access modes and to increase the speed of the device, adders, one-shot, decoder and delay element, the inputs of the higher bits of the counters-registers are the inputs of the higher bits of the device address, the synchronization inputs of the device's synchronization input, and the counting inputs and input of the delay element of the device's inversion, the inputs of the lower bits of one counter-register are connected to one the inputs of the adders and are the inputs of the lower bits of the device address, and the inputs of the lower bits of the other counters are connected to the outputs of the corresponding adders whose inputs are the installation inputs of the device, one of the inputs The connectors are connected to the output of the delay element, some of the outputs are connected to the inputs of the corresponding single vibrators, and the other outputs are connected to the corresponding outputs. the decoder, the inputs of which are connected to the outputs of the bits of the corresponding counter-register, the inversion inputs of the memory blocks are connected to the outputs of the corresponding single-oscillators, and the write (read) inputs are the write input of the device.