SU1283948A1 - Device for determining position characteristics of non-position code - Google Patents

Abstract

 Device,; for determining the positional characteristics of a non-positional code, it is in the field of computing technology and can be used in information processing and transmission systems using modular codes. The aim of the invention is to expand the scope of use due to the possibility of calculating the number kernel. This goal is achieved by the fact that a device containing a binary adder, a modulo adder, two constant storage units, a switch, a synchronization unit and a shift register, contains a constant multiplication and summation unit as well as due to the corresponding links between the existing and the entered units. The technical advantage of the claimed invention lies in the possibility of determining, together with the rank of the number, one more positional characteristic, the number kernel. 1 hp f-ly, 4 ill. 4 tab. (L

Description

1 12

 The invention relates to computing and can be used in information processing and transmission systems using modular codes.

The purpose of the invention is to expand the scope of application due to the possibility of calculating the core number.

FIG. 1 shows a block diagram of a device for determining the positional characteristic of a non-positional code; FIG. 2 is a diagram of the synchronization unit: in FIG. 3 is a block multiplication and constant block diagram; Fig. 4 is a timing diagram of the formation of signals by a synchronization unit.

The device for determining the positional characteristics of the non-positional code (Fig. 1) contains a shift register 1, blocks 2 and 3 for storing constants, switch 4, binary adder 5, modulator 6, unit 7 / multiplication by constant and summation, block 8 synchronization, information input 9 of the device, outputs 10 and 11, device rank and core, clock input 12 of the device, inputs 13 and 14 of the start and reset of the device, outputs ISIS of the synchronization unit 8. The synchronization unit 8 (FIG. 2) contains the triggers 20-22, the distributor 23 impulse

owls, counter 24 modulo, decoder 25, elements And 26-28, elements 29-31 delay.

The multiplier per constant and summation unit 7 (FIG. 3) contains multipliers 32-34 per constant modulo and adder 35 modulo.

In the operation of the device, the following is used to determine the positional characteristics of the non-positional code.

Any positive integer N can be represented in the system of bases p,, p,

35

40

R.

at; pn

t g rm

Vp; r-.np.-;

we get that

..

PCh.1

(7)

Where

 (| (1)) (Shoar ,,, -); 0 (Pp- ()) (inodp ,,).

p residues o, oi.,, ...,,

It can be transferred to the positional number system according to the following expression

N - g, P „,

Thus, substituting (7) in C3), 45 we obtain the rank of the number 2y and also calculate the core of the number Rf.

To reduce instrumentation costs.

where K is ta - 2m.

(one)

where r „rat choose p, something that p„ ,. pp p. 50 This provides a calculation using a binary adder.

Constant constants blocks 2 and 3 can be made on EPROM or commutators with fixed constant codes; In blocks of the temple.

no constants recorded codes of the set of constants // b; oi .; / J, and / Rg; ot; / respectively addresses to which residual codes are ot; and code norang number j p

R"

no j numbers

tz. ™ - RP with:

O, - :: base numbers, odP

uniquely corresponding to the base system; t. - comparison solution

Н1 (mod.p;).

Expand the base system by adding an excess base p „,, then

n, N modp +

li Р „

and designating / -

RP.

Hi RI.

(2)

- / 3; ,

will get

FP4

R

- - k

 | - n +,

4 - // ft «, ;;., -... + / P.,.,.,.

РГPni .i pnfi

where

(, о., + ... (. + 0К (tpoar „„)), (4) where b; and 0 are the coefficients defined by the system of bases, N is the number of numbers defined as

B4

Prin in €, t; 2 ... 0 iHz 1,

(6)

, OC, + ... (. N (mod R),

Where

.

pn

R t g rm

Vp; r-.np.-;

we get that

..

PCh.1

(7)

Where

40

 (| (1)) (Shoar ,,, -); 0 (Pp- ()) (inodp ,,).

Thus, substituting (7) in C3), 45 we obtain the rank of the number 2y and also calculate the core of the number Rf.

To reduce instrumentation costs.

where K -

R,. t calculation about adder.

312839484

measure of remainder i. For the case of P, 3, P Constant storage unit 3 has 5, constant storage unit 2 has the encoding shown in Table. one.

encoding presented in table.

 The constant storage unit 3 has

encoding presented in table. 2

Binary adder 5 and adder 6 modulo Rj3 are accumulating with the possibility of zeroing.

Block 7 converts the residual code and the R code into a value code Note. It means that according to (7), the capacity of the cells can be fulfilled in a particular case can be arbitrarily 20 on an EPROM, which has the following encoding for the case presented in Table. 3

using the following table. 4 truths. the delay element 29 is connected to the table 3

to the left input of the trigger 21, the second output - through 3. Delay 30 is connected to the zero input of the trigger 22, and the third to the zero input of the trigger 20.

A device for determining the positional characteristics of a non-positional code works as follows. In the initial state, the pulse at the reset input 14 will write down the codes of the residuals Qd, - uin shift register 1, reset adders 5, and 6, counter 24, reset the distributor 23 and triggers 21 and 22 to the initial state. First input of switch 4 . - the output of its output by supplying the potential of logic 1 from the output of the trigger 5a 22 to the control input B, which results in the first; the inputs of blocks 2 and 3 of the storage of the constants from the output of the counter ygg 24 receive the zero code, and code of the minor remainder is,.

After a time equal to the duration of the transitional processes, 5 the codes of the magnitude / I, odi / n and I about I appear at the outputs of blocks 2 and 3 of the stored-1 and constants

 respectively, arriving at the inputs from; ummators 5 and 6,

With npHxoAOrvi pulse Start at input 13 start, the device at the output of the trigger 20, the potential of a logical unity): 5 which will allow the clock impulses (TI) from input 12 to pass through the element I 26. With the arrival of the first TI, the distributor 23 pulses generates the first 7 - And the first phase, which is on the second output 16 and the fifth output 19 of block 8 and snaps into the value codes in tori 5 and 6, respectively

With the arrival of the next TI, the distributor 23 of the pulses generates the TI of the second phase, which is. Wits on the first exit. 7 of block 8 and will shift the content of the regmestra 1, t, e „at its output according to the Vits code of the remainder, i, and will change the code value of the number of

ka 1.

older weekend tires

counter 24; 7; unit code, where K is the number of counter bits. Thus, after the end time of the transient processes at the output of blocks 3 and 2, the storage of constants is in terms of the codes of values //., Ыгр, and /RBj.o -i / Rn, respectively. The second TI of the first phase will increase the binary sum sum.

50

five

0

five

0

five

0

five

mators 5 and 6 for the indicated code values.

Further, the work process is similar to that described.

2 (n-1) -th TI-will shift the contents of register 1, as a result of which, at its output, according to the Vits code, the higher remainder, {, 5, will also change the state of the counter 24, at its higher output buses, the code of the number of the higher base will be - one. At the first output of the decoder 25, a positive pulse is generated, which, via delay element 29, will reset trigger 21 to the zero state, resulting in inhibiting the register contents I. The delay is necessary to eliminate the possibility of cutting the last clock pulse shifting the contents of register 1. With the arrival of the next TI, the distributor 23 pulses generates the TI of the second phase, which will change the contents of the adders 5 and 6 by the values

. ,, ,, J, respectively. At the exit of the north-west trap 6, i.e.

output 11 of the device will form

The code is the drama of the number. In addition, the code of 2-1 from the output of the counter 24 triggers the light on the second output of the decoder 25 of the pulse, which, through the delay 30, sets the trigger 22 to the zero state, as a result of which the TI of the first phase, changing the contents, is forbidden. adder 6. A delay is necessary to eliminate the possibility of cutting the last TI of the first phase, which changes the content of adders 5 and 6,

The zero potential from the output of the trigger 22 is connected to the second input of the switch 4 to its output. Since there are no code changes from the moment triggers 21 and 22 are set to the zero state. and at the outputs of the shift register a 1 and adder 6, then at the output of block 7. through the time of completion of the transient processes, the code of magnitude / | 8 is obtained (x; /, / p which through the switch 4 enters the input of the binary su-matr 5 The last TI causes the appearance at the first output of the distributor 23 of TI pulses of the first phase, which snaps into the indicated one; the code B of the binary adder 5, the output code of the number rank is set on its output.

In addition, the last TI causes the appearance at the third output of the decoder 25 of a pulse, which sets the trigger 20 to the zero state and closes

element And 26, stopping the passage of TI. The operation of the device ends there.

Claims (2)

1. A device for determining the positional characteristics of a non-positional code, comprising a binary adder, a modulo adder, two constant storage units, a switch, a synchronization unit and a shift register, the information input of the device connected to the information input of the shift register whose reception input input is connected to inputs of zeroing of the binary adder and modulo adder and with the device reset input, the clock input of the start and reset inputs of which are connected respectively to the inputs of the synchronization unit, p The first output of which is connected to the higher bits of the address input of the first and second storage units of constants, the lower bits of the address input of which are connected to the output of the shift register, the output of the first storage unit of the constants connected to the first information input of the switch, the output of which is connected to the information input of the binary adder, the output of which is the output of the device rank, the second, third, fourth and fifth outputs of the synchronization unit are connected according to 1283948., with the clock inputs of the binary adder and shift register, the control input of the switch and the clock input of the modulo adder, characterized in that, in order to expand the scope of use due to the possibility of calculating the number core, it contains a multiplication unit by a constant and a summation, with the output of the second storage unit of constants connected to the information input of the modulo, the output of the device core, the outputs of the shear the register and the modulo adder are connected respectively to the first second inputs of the block of multiplication by a constant and summation, the output of which is connected to the second information input of the switch. 2. A device according to claim 1, characterized in that the multiplication unit per constant and summation comprises three multipliers per constant modulo and modulo adder, the first and second inputs and the output of the multiplication unit per constant and summing are connected respectively to the inputs of the first and second the second multipliers on a constant modulo and with the output of the third multiplier on a constant modulo, the outputs of the first and second multipliers on a constant modulo are connected respectively to the inputs of the first and second term modulo adder o is connected to the input of the third multiplier by a constant modulo. . in It3 Irv w ScmiHoSxo F  Start U I L TH J2 A PPP PP-Y-P Fig.Z