RU2012041C1 - Device for computing sums of pair products - Google Patents

Abstract

FIELD: computer technology. SUBSTANCE: device has error correction unit 12, module adder 13, unit 3 for computing sums of pair products for control base. The units provide detection and correction of single errors for operational bases. EFFECT: improved failure-free operation. 2 cl, 1 tbl, 1 dwg

Description

 The invention relates to computer technology and can be used in signal processing processors, in digital filters, etc.

 The purpose of the invention is to increase the fault tolerance of the device for calculating the sums of paired products.

 The invention consists in the following.

 The main advantage of the system of residual classes (RNS) is the independence of the formation of digits of the number, whereby each digit carries information about the entire initial number. This implies the possibility of their parallel processing. This allows you to attract new methods of arithmetic control. With the introduction of an additional control base, the balance taken on this base carries redundant information about the original number, which allows you to detect and correct errors in numbers on working grounds.

-rP_n, (1) где β_i - ортогональные базисы;
r - ранг числа;
P_n=

p_i - полный диапазон (2);
p_i - основания СОК, i=

;
n - число рабочих оснований;
P_n+1 - контрольное основание.Any number N represented in the RNS as N = (α ₁ α ₂ ... Α _n , α _{n + 1} ) can be expressed as
N =

-rP _n , (1) where β _i are orthogonal bases;
r is the rank of the number;
P _n =

p _i is the full range (2);
p _i - the base of the RNS, i =

;
n is the number of working bases;
P _{n + 1} - control base.

p_i·p_n+1= Р·p_n+1, (3) где Р - рабочий диапазон.In the same time
P _n =

p _i · p _{n + 1} = P · p _{n + 1} , (3) where P is the operating range.

= 0, (4) где S - номер интервала, в котором находится число N.The number N is considered correct if N <P. In other words
S =

= 0, (4) where S is the number of the interval in which the number N.

=

- rp_n+1=

. (5)
Известно, что β_i= РR_i+ A_i, где R_i=

; A_i - остаток от деления.We substitute equality (1) into equality (4), then
S =

=

- rp _{n + 1} =

. (5)
It is known that β _i = PR _i + A _i , where R _i =

; A _i is the remainder of the division.

But A _i = β _i ^I , where β _i ^I is the orthogonal basis with base p ₁ , p ₂ . . . p _n .

+

Но

= r′ - ранг числа в системе по рабочим основаниям P₁, P₂, . . . P_n.We substitute the obtained equalities into formula (5), then
S =

+

But

= r ′ is the rank of a number in the system for working reasons P ₁ , P ₂ ,. . . P _n

Since the selected system is ordered (P ₁ <P ₂ .. <P _n <P _{n + 1} ) and the quantity P _{n + 1} > 2P _n P _n-1 , the value Δ of the result correction can be uniquely determined from the value of S. For example, suppose we have a base system P ₁ = 3, P ₂ = 5, P ₃ = 31. (control base P ₃ ).

p_i= 3·5·31= 465;
Р= p₁·p₂= 3·5= 15.Then P _n =

p _i = 3 · 5 · 31 = 465;
P = p ₁ · p ₂ = 3 · 5 = 15.

We calculate the orthogonal bases
β ₁ = 310; β ₂ = 186; β ₃ = 435.

= 15·20+10;
β₂= 15·R₂+

= 15·12+6;
β₃= 15·R₃= 15·29.We calculate the coefficients
β ₁ = 15 R ₁ +

= 15 · 20 + 10;
β ₂ = 15 R ₂ +

= 15 · 12 + 6;
β ₃ = 15 · R ₃ = 15 · 29.

We get
R ₁ = 20, R ₂ = 12, R ₃ = 29, β ₁ ^I = 10, β ₂ ^I = 6
Take N = 8. In the RNS, it has the form N = (2, 3, 8).

+20·2+12·3+29·8

= 0.Calculate the value
S =

+ 20 · 2 + 12 · 3 + 29 · 8

= 0.

Suppose that an error has occurred and the number N ^I = (1, 3, 8) has been obtained.

+20·1+12·3+29·8

= 10.Then
S =

+ 20 · 1 + 12 · 3 + 29 · 8

= 10.

:
N_ист=

+

.In accordance with the value of S applied to the memory input, a number appears on the memory output, which must be added to

:
N _East =

+

.

 In our example, the memory works according to the table.

= 13, N_ист=

13+10

= 8.According to the table in the first example, we have
N = 8, N _East = 8 + 0 = 8,
in the second example

= 13, N _East =

13 + 10

= 8.

 The bug is fixed.

 In FIG. 1 shows a functional diagram of a device for calculating the sums of paired products; in FIG. 2 is a functional block diagram of the error correction block.

 A device for calculating the sums of paired products (Fig. 1) contains blocks for calculating paired products for arbitrary module 1, 2 and control module 3, each of which contains a register 4, memory 5, matrix adder 6, matrix multiplier 7 and three groups of buffer registers 8, 9, 10, a code converter 11 for the RNS code into a positional code, an error correction unit 12, a modular adder 13, a clock counter 14 and an output 15 of the result of the device.

 The error correction block 12 (Fig. 2) contains four registers 16-19, a switch 20, two matrix multipliers 21, 22, a modular adder 23, a counter 24 clock transitions, three memories 25, 26, 27, information inputs 28, 29, 30 , 31 blocks, output 32 of the block and input 33 of the resolution of the block.

 The memory, matrix multipliers, matrix adders in the device are made in the form of read-only memory (ROM).

 The device operates as follows.

 In the information registers of 4 blocks 1, 2, 3, before starting work, numbers are written in the code of the RNS. The clock counter generates addresses for reading coefficients, which are stored in blocks 1, 2, 3 in memory 5 in the code RNS. The contents of registers 4 in each of blocks 1, 2, 3 are multiplied with the coefficients using matrix multipliers 7. The result of the multiplication is written to the first group of buffer registers 8, the contents of which are added to the contents of the buffer registers 10 of the third group (addition to zero in the first cycle) . Addition is carried out by matrix adders 6 in each of blocks 1, 2, 3. The sum is written into buffer registers 10 of the third group. From the outputs of the buffer registers 10 of blocks 1 and 2, the result is fed to the inputs of the converter 11 of the RNS code into a positional code and to the information inputs of the error correction block 12, the third input of which also contains information from the outputs of the buffer registers 10 of block 3. The clock counter at the end of the pairing works gives an enable signal to the input of the resolution of the Converter 11 and the block 12 error correction. From the second output of the converter 11 to the fourth input of the error correction block 12, a signal is received about the transition through R. The structure of the converter 11 is similar to the prototype. The results from the outputs of the Converter 11 code RNS into a positional code and block 12 error correction are fed to the inputs of the modular adder 13, where the addition occurs. The output of the modular adder 13 is the output of 15 devices. The components of the SOK code in the information registers of 4 blocks 1, 2, 3 can be written from an analog-to-digital converter.

 Block 12 error correction works as follows.

The values of α ₁ , α ₂ and α _{3 are} recorded in the corresponding registers 16, 17, 18. The values of α _{1 and} α _{2 are} sequentially supplied through the switch 20 to the multiplier 21, the second of which receives the value R ₁ and R ₂ from the memory output 25 of the ROM. The value of α ₃ from the output of the register 18 is supplied to the matrix multiplier 22, where α ₃ ˙ R _{3 is} multiplied. The values α ₁ ˙ R _{1 and} α ₃ ˙ R ₃ are fed to the input of the modular adder 23, where they add up. The result is entered in register 19. Then this result, which is intermediate, is fed to the input of the adder 23, where it is summed with the value α ₂ ˙R ₂ . The result is entered in register 19, and then fed back to the input of the adder for addition with a value of r ^I , which is supplied from the output of the counter 24 of the number of transitions. The final result is input to the memory 26, at the output of which a correction value appears, which is fed to the output 32 of the error correction block.

Claims (2)

 1. A DEVICE FOR CALCULATING THE SUM OF PAIRED WORKS, containing a code for the RNS code into a positional code, a clock counter and two blocks for calculating paired products on an arbitrary basis, each of which contains a register, memory, matrix multiplier, three groups of buffer registers and a matrix adder, and the output the clock counter is connected to the addressable memory inputs of the first and second blocks for calculating the sums of paired products on an arbitrary basis and the input of the resolution of the operation of the code converter code for positional code, and each of the blocks for calculating the sums of paired products by an arbitrary module, the output of the register is connected to the first input of the matrix multiplier, the second input of which is connected to the memory output, and the outputs to the inputs of the buffer registers of the first group, the outputs of which are connected to the inputs of the first term of the matrix adder, the outputs of which are connected with the inputs of the buffer registers of the second group, the outputs of which are connected to the inputs of the buffer registers of the third group, the outputs of which are connected to the inputs of the second term of the matrix adder and with responsibly with the first and second information inputs of the code converter into a positional code, characterized in that an error correction unit, a modular adder and a unit for calculating the sums of paired products on a control base, consisting of a register, memory, matrix multiplier, matrix adder and three groups of buffer registers, and the output of the clock counter is connected to the address input of the memory of the unit for calculating the sums of paired products on the control base and the input of the resolution of the operation of the error correction unit, the path of which is connected to the input of the first term of the modular adder, the input of the second term of which is connected to the first output of the RNS code converter into a positional code, and the output is connected to the output of the result of the device, and in the block for calculating the sums of paired products on the control base, the register output is connected to the first input of the matrix a multiplier, the second input of which is connected to the memory output, and the outputs to the inputs of the buffer registers of the first group, the outputs of which are connected to the inputs of the first term of the matrix adder, the outputs of which are connected to the inputs of the buffer registers of the second group, the outputs of which are connected to the inputs of the buffer registers of the third group, the outputs of which are connected to the inputs of the second term of the matrix adder and the first information input of the error correction block, the second and third information inputs of which are connected respectively to the outputs of the buffer registers of the third group the first and second blocks for calculating the sums of paired products on an arbitrary basis, the second output of the code-to-position code converter is connected to the even the fourth information input of the error correction block.  2. The device according to p. 1, characterized in that the error correction block contains four registers, a switch, three memories, two matrix multipliers, a modular adder and a transition number counter, the output of which is connected to the first input of the modular adder, the second and third inputs of which are connected respectively, with the outputs of the first and second matrix multipliers, the first inputs of which are connected respectively to the outputs of the first and second memory, the address inputs of which are connected to the input permitting the operation of the unit and the control input of the switch, the second and second information inputs of which are connected respectively to the outputs of the first and second registers, the inputs of which are connected respectively to the second and third information inputs of the block, the first and fourth information inputs of which are connected respectively to the inputs of the third register and counter of the number of transitions, the output of the modular adder is connected to the input register, the first output of which is connected to the fourth input of the modular adder, the output of the block is connected to the output of the third memory, the address input of which is connected to eye output register.

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