SU1282333A1 - Shaft turn angle-to-digital converter - Google Patents

Abstract

The invention relates to the field of automation and computing and can be used to connect analog information sources with a digital computing device. In order to increase the stability of the converter by eliminating variations in the results of the conversion to the converter containing the phase shifter, the first and second null organs, the trigger, the pulse generator, the first AND element, the counter, the first register, the power bus, the second register, the subtractor, the comparison unit, the second And element, delay element and code bus setpoint. At the output of the phase shifter, an alternating current signal is formed that is out of phase with respect to the power bus signal by an angle f. At the output of the trigger, a time interval is formed, the duration of which is proportional to the angle V. In the counter, a code is generated that is proportional to the time interval. The current count counter code is written to the first register and compared with the previous count code recorded in the second register. If the difference between the codes of the current and the preceding samples in the module is greater than the setpoint code, the pulse from the second output of the delay element rewrites the code from the first register to the second. The delay element is designed to generate three control-pulses from the input signal of the second comparator. 1 PC. from 3 th

Description

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The invention relates to automation and computer technology and can be used to communicate anapogue information sources with a digital computing device.

The aim of the invention is to increase the stability of the converter by eliminating variations in the results of transformations.

The drawing shows a block diagram of the Converter.

The converter contains phase shifter 1, first 2 and second 3 zero-organs, trigger 4, generator 5 pulses, first element 6, counter 7, 11: first 11 and second 9 registers, calculated 10, block 11 comparison, second e..hement and 12. delay element 13, power supply, bus 15 setpoints

The converter works in the following way - liu-iM.

At the input of the phase shifter 1, an alternating current signal is generated that is shifted in phase with respect to the power bus signal 1 by an angle ip proportional to the rotation angle d of the phase shifter rotor 1. Zero organs 2 and 3 for-g are generated by rectangular pulses from FRON. TOV which triggered trigger 4,

At the trigger output. 4, BP is formed (an interval whose duration is proportional to the rotation angle oL of the phase shifter 1. The pulses from the output of the generator 5 temporarily fill the interval with the element And 6. The number of pulses, also proportional to the rotation angle of the phase shifter 1, enters the formation 7 input of the counter. The parallel code of the counter 7 with the pulse from the first output of the delay element 13 is rewritten into the register 8 through the code set time in the counter 7.

The counter size .7 is selected greater than the required bit width of the converter n by the value of yp, which is determined. from the condition of the maximum instability of the time interval at the output of the trigger 4 and the unstable frequency generator of 5 pulses. At the same time, the period of the pulse generator .5 should be less than the magnitude of the time interval.

The rotation of the phase shifter 1. On either side, the code from the outputs of registers 8 and 9 is fed to the inputs of the subtractor 10, which determines by what amount the codes in registers 8 and 9 differ from each other. The output code of the subtractor 10 is fed to one group of inputs comparison unit 11, where it is compared with the bus installation code 15. If the modulus code of the difference between the codes of registers B and 9 is greater than the set code, then a logical level is formed at the output of the comparison block 11 that permits the passage of a pulse from the second element 13 through the element 12. code from register 8 rewritten to register 9 and the angle code

rotation is fed to the output of the converter. The impulse from the third output of the delay element 13 has zeroed the counter 7.

If the input axis is stationary, then the number of pulses at the output of the element. 6 can be changed by a value not exceeding the converter instability, and the module code of the difference between the codes of registers B and 9 is less than the set code from the busbars 15. At the output of the comparison unit 11, a level is formed that prohibits the passage of a pulse from the second output of element 13 through element 12 at the input of register enable 9. The register output 9 will remain constant. Thus, a digital hysteresis is introduced into the converter, by which the output code spreads from one conversion cycle to another is eliminated. .

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Claims (1)

Invention Formula 45 Converter angle of rotation of the shaft in the code containing the phase shifter, input and. the output of which through the first and second zero-organs are respectively connected to the trigger inputs, the trigger output and the pulse generator output are connected to the inputs of the first element AND whose output is connected to the information input of the counter, the outputs of the counter bits are connected to the information inputs of the first register , a power bus connected to the input of the phase shifter, characterized in that, for the purpose of increasing stability of the converter, a second register, a subtractor, a comparison unit, a second AND element, a delay element and dovye tires the settings, the outputs of the bits of the first register are connected to the information inputs of the second register and to one group of inputs of the subtractor, the other group of inputs of which is connected to the outputs of the bits of the second register, the outputs of the subtractor and code buses of the settings are connected respectively to one and the other groups of inputs of the comparison unit the output of which is connected 12823334 to one input of the second element And, the output of the second element And is connected to the control input of the second register, the output of the second null organ is connected to the input of the delay element, the first, second and third outputs of which are connected respectively to the control input of the first register, another input of the second element AND fO and to the installation inputs of the counter. P / fffi