SU1270875A1 - Digital band-pass filter - Google Patents

Abstract

The invention relates to a pulse technique. Can be used for frequency filtering of signals. The purpose of the invention. - Improving the speed and reliability of the device, achieved through constructive simplification. The device contains an amplifier limiter I, a generator of 2 clock pulses, a counter of 4 pulses, selectors 5 and 6 of the lower and upper frequency, trigger 7, the element IS-HE 8, the input bus 9 and the output bus 10. Constructive simplification of the device is achieved by introducing the element HE 3 into it The increase in speed realized by this device also made it possible to increase the noise immunity of the filter in comparison with the prototype, in particular in those cases when the signal fluctuates at the edge of the filter bandwidth. Reducing the number of logic elements, I implementing this design, ensures that the device reduces the weight and dimensions of the device. 4 Il. JO N9 8 O 00 cf

Description

The invention relates to a pulse technique and is intended for frequency filtering of signals.

The aim of the invention is to increase the speed and reliability 5 of the device due to its structural simplification. .

Figure 1 presents the structural diagram of a digital band-pass filter; figure 2, 3 and 4 are diagrams explaining 1® explaining his work,

The device contains (Fig. 1) an amplifier-limiter 1, a clock generator 2, an element 3 NOT, a counter 4 pulses, selectors 5 and 6 of them, 15 and the upper cut-off frequency, trigger 7, element 8 AND NOT, the input bus 9 output bus 10.

The input of the amplifier-limiter is connected to the input bus 9, and the output ^{20 is} connected to the input of the element 3 NOT, as well as. the third input of the trigger 7, and the output of the element 3 is NOT connected to the first input of the element 8 AND NOT

4 · ”25, the first input of which is connected to the output of a 2-clock generator! pulses, and the outputs are connected to the inputs of the selectors 5 and 6 of the lower and upper cutoff frequencies, the outputs of which are respectively ³⁰ connected to the second and first inputs of the trigger 7, the output of which is connected to the second input of the element 8 AND NOT, the output of which is connected to the output bus 10. 35

The device operates as follows.

If the frequency of the input signal is in the predetermined filter pass band (Fig. 2b), the pulses generated by the amplifier-limiter 1 (Fig. 2c) are fed to the input of the element 3 NOT, on which they are inverted (Fig. 2f) and fed to R input. counter 4. The counting input of the counter ⁴ 5 4 receives pulses from the generator 2 clock pulses (Fig. 2 a) .. As a result, the outputs of the counter 4 generates a code proportional to the period of the input signal. When 50 passes the signal of the upper cutoff frequency, the selector 6 generates a pulse (Fig. 2 g), which sets the trigger 7 in a single state (Fig. 2 e). Initially, the trigger 7 is set to a zero state by the leading edge of the signal. The control signal from trigger 7 is fed to the input of AND-NOT element 8, to the other input of which an inverted input signal is supplied (Fig. 2 e). The signal repeats the input signal on the output bus U of the digital filter (Fig. 2 g). In FIG. 2 h shows the input signal with the upper cutoff frequency.

If the frequency of the input signal is lower than the lower boundary passband of the filter (Fig. 3a, b), the trigger 7 is in the zero state (Fig. 3d) when receiving a control pulse from the selector 6 of the upper cutoff frequency (Fig. 3 is set When the input signal passes the lower cut-off frequency, the selector 5 of the lower cut-off frequency generates a pulse (Fig. 3 c), which sets the trigger 7 to the zero state (Fig. 3 g), which prevents the appearance of the input signal at the output of the filter (Fig. 3 e) subject to inverted input signal (Fig. 3 e). Fig. 3 g of the input signals are shown with a lower and upper boundary frequency.

If the frequency of the input signal is higher than the upper limit of the filter passband (Fig. 4 a), the trigger 7 along the edge of the signal from the output of the amplifier-limiter (Fig. 4 b) will be set to zero (Fig. 4 g) and remain in it, since the selector 6 will not give out an impulse, setting the trigger 7 in a single state. Thus, the passage of the signal through the element 8 INE is excluded (Fig. 4 e) taking into account the inverted input signal (Fig. 4 e). In FIG. (4 V) shows the input signal with the upper cutoff frequency.

Claims (1)

The invention relates to a pulse technique and is intended for frequency filtering of signals. The aim of the invention is to increase the speed and reliability of the device due to its structural simplification. Figure 1 shows the block diagram of a digital bandpass filter; FIGS. 2, 3 and 4 are diagrams explaining his work. The device contains (FIG. 1) limiting amplifier 1, generator 2 of such pulses, element 3 NOT, counter 4 pulses, selectors 5 and 6, and the upper cutoff frequency, three ger 7, element 8 NAND, input bus 9, the output bus 10, Input, the amplifier-limiter is connected to the input bus 9, and the output is connected to the input of element 3 NOT, as well as to the third input of trigger 7, and the output of element 3 is NOT connected to the first input of element 8 AND-NOT and to the second input of counter 4, the first input of which is connected to the generator output 2 clock; pulses, and you ™ are connected to the inputs of selectors 5 and 6 of the lower and upper boundary frequencies, the outputs of which are respectively connected to the second and first inputs of trigger 7, the output of which is connected to the second input of element 8 IU, the output of which is connected to the output bus 10, the device operates as follows. If the frequency is found, the input of the signal in the specified filter bandwidth (Fig. 2b) is generated by the amplifier 1 limiter and the pulses (Fig. 2c) are input to the element 3 which is not inverted. (|) iGo 2 e) and act The counters input of counter 4 receives pulses from the generator 2 clocks of pulses (FIG. 2 a). As a result, the outputs of counter 4 form a code proportional to the period of the input signal. When the upper limit frequency is passed by the selector 6, a pulse is formed (Fig. 2 g), which sets trigger 7 to one state (Fig 2d). Initially, trigger 7 is set to zero state. Controller4 signal from trigger 7 is fed to the input of element 8 AND-NOT, to the other input of which an inverted input signal arrives (Fig. 2e). On the output bus 10 of the digital filter, the signal repeats the input signal (Fig. 2 g). Fig. 2 3 shows an input signal with an upper cutoff frequency. In case the frequency of the input signal is lower than the lower filter bandwidth (Fig. Per, b), trigger 7, which is in zero state (Fig 3g), when receiving a control pulse from the selector 6 of the upper boundary frequency ( Fig. 3 c) is set to one. When the input signal passes the lower cutoff frequency, the selector 5 of the lower cutoff frequency generates a pulse (Fig. 3c), which sets the trigger 7 to the zero state (Fig. 3g) 5, which prohibits the appearance of the input signal at the filter output (Fig. 3 f) taking into account the inverted input signal (Fig. 3 d) “In Fig. 3, the input signals are shown with the lower and upper frequency boundaries. If the frequency of the input signal is the upper limit bandwidth of the filter (Fig. 4a), trigger 7 on the front of the signal from the output of the limiter (Fig. 4b) will be set to zero (fig 4) and will remain in it, since the selector 6 does not have a pulse that sets trigger 7 into a single state. Thus, signal passing through element 8 AND is NOT excluded (FIG. 4 e) with regard to the inverted input signal (FIG. 4 d) o FIG. (4 c) shows an input signal with an upper cutoff frequency; Invention A digital bandpass filter containing a clock pulse generator, the output of which is connected to the first input of a pulse counter, the outputs of which are connected to the inputs of the upper and lower cutoff frequency selectors, the outputs of which are connected respectively to the first and second inputs of the trigger, as well as the NAND element, the output of which is connected to the output bus, and the amplifier limiter, the input of which is connected to the input bus, o t - characterized by the fact that, in order to improve speed and reliability, an element NOT is introduced into it, the input of which is connected to the output of the amplification of the limiting device and the third input trigger, and the output of the element is NOT connected to the second input of the pulse counter and to the first input of the element, the second input of which is connected to the trigger trigger. V t well eleven at P g 1C yx (pus. 2 11 P