SU1269241A1 - Pseudorandom sequence generator - Google Patents

Abstract

The invention can be used to test high-speed logic circuits. The aim of the invention is to increase reliability. To achieve the goal, a single pulse generator 2 and a switch 3 are entered into the pseudo-random sequence generator. The generator also contains 1 clock pulse generator, register 4, adders 5, 6, 8 modulo two, delay element 7. This pseudo-random sequence generator allows not only reducing hardware costs, but also simplifying the procedure for synthesizing generators of pseudo-random sequences (L tot. 1 Cp f-ly, 1 ill. Is :) O) with tc 1

Description

The invention relates to a pulse technique.

The aim of the invention is to increase the reliability of the pseudo-random sequence generator.

The drawing shows a functional diagram of a pseudo-random sequence generator.

The pseudo-random sequence generator comprises a clock pulse generator 1, a single pulse generator 2, a switch 3, a register 4, the first and second adders 5 and 6 modulo two, the delay element 7, the third adder 8 modulo two. The outputs of the clock generator 1 and the single pulse generator 2 are connected respectively to the second and first inputs of the switch 3, the first and second outputs of which are connected respectively to the second and fourth inputs of the register 4, the fourth and fifth outputs of which are connected respectively to the first and second inputs of the first adder 5 modulo two, the output of which is connected to the third input of the register 4, the second and third outputs of which are connected respectively to the first and second inputs of the second adder 6 modulo two, the output of which connected to the first input of the register 4, the first and sixth outputs of which are connected respectively to the second, the input of the third adder 8 modulo two and the input of the delay element 7, the output of which is connected to the first input of the third adder 8 modulo two.

Register 4 contains w D-flip-flops

9.1 ... 9.sh. The information input of the first D-trigger 9.1 is connected to the third input of register 4, the first input of which is connected to the information input of the second D-trigger 9.2. Information input of the 1st D-flip-flop

9.1 is connected to the output of the (i-2) -ro D trigger 9.1-2 (1 = 3, w). Installation inputs m D-flip-flops 9.1 ... 9. Ш are connected with each other and with the second input of register 4, the fourth input of which is connected to the synchronization inputs m D-flip-flops 9.1 .., 9.m. The outputs of the (j_1) _th _and j-ro D-flip-flops 9.j ~ 1 and 9.j are the fourth and second outputs of register 4, respectively. (j = 2, m), the sixth and first outputs: which are connected respectively to the outputs of (k-l) -ro and the k-th D-flip-flops 9.k-1 and 9.k (k = 2, t). The outputs of the (t-1) th and th th D-flip-flops 9.t-1 and 9.t are the fifth and third 5 outputs of the register, respectively.

The pseudo-random sequence generator operates as follows.

ί Λ

In the initial state, register 11 is written to register 4 by means of a signal from the output of a single pulse generator 2 and switch 3 ... With the arrival of the first clock pulse of ¹⁵ s, from the output of a clock pulse generator 1, the 1st D-trigger 9.1 of register 4 receives information from (i-2) -ro D-flip-flop 9.1-2 (1 = 3 ', pi). The first adder 5 modulo two generates a signal for the first D-trigger 9.1 of register 4, and the second adder 6 modulo two for the second D-trigger 9.2 of register 4. With the arrival of the following pulses at the outputs of m D-triggers 9.1-9. In register 4, pseudorandom sequences are formed, determined by the generating polynomial. Moreover, the sequence generated at the output of the k-th D-flip-flop 9.k- ^{30 of} register 4 is shifted relative to the sequence generated at the output of the (k-1) -th D-flip-flop 9.k-1 of register 4 by [N / 2J where N is the period of the pseudo-random sequence, k = 2, t. Thus, copies of the pseudo-random sequence shifted by [K / 2J are formed in adjacent bits of register 4, and using delay element 7, the shift is performed by N / 2. Further summing up these two copies of the pseudo-random sequence on adder 8 modulo two, we obtain at its output a pseudo-random sequence with doubled frequency.

Claims (2)

The invention relates to a pulse technique. The purpose of the invention is to increase the reliability of the pseudo-random sequence generator. The drawing shows the functional diagram of the generat pseudo-random sequence. The pseudo-random sequence generator contains a generator of 1 clock pulses, a generator of 2 single pulses, switch 3, register 4, the first and second adders 5 and 6 modulo two, delay element 7 and the third adder 8 modulo two. The outputs of the clock generator 1 and the generator 2 of a single pulse are connected respectively to the second and first inputs of the switch l 3, the first and second outputs of which are connected respectively to the second and fourth inputs of the register 4, the fourth and fifth outputs of which are connected respectively to the first and second the inputs of the first adder 5 modulo two, the output of which is connected to the third input of the register 4, the second and third outputs of which are connected to the first and second inputs of the second adder 6 modulo two, the output of which It is connected to the first register input. 4, the first and sixth outputs of which are connected respectively to the second input of the third adder 8 modulo two and the input of the delay element 7, the output of which is connected to the first input of the third adder 8 modulo two. Register 4 contains m D-flip-flops 9.1 ... 9.m. The information input of the first D-flip-flop 9.1 is connected to the third input of register 4, the first input of which is connected to the information input of the second D-flip-flop 9.2 Information input of the i-ro D-flip-flop 9.1 is connected to the output of () ro Dtrigger 9.1-2 (, t). The setup inputs m D-flip-flops 9.1 ... are connected to each other and to the second input of register 4, the fourth input of which is connected to: synchronization m of m D-flip-flops 9o1 .., 9.m, Outputs () th and j-ro D-flip-flops 9.J-1 and 9.J are respectively the fourth and second outputs of register 4, (, m), the sixth and first outputs: which are connected respectively to 1 (kl) -ro and k-ro D-flip-flops No. k-1 and 9, k (, m). The outputs (in-l) -ro of the m-th D-triggers 9.m-1 and 9.iii are, respectively, the fifth and third outputs of the register. The pseudo-random sequence generator runs as follows. In the initial state, the code 1 1 ... 1 is written to the register 4 by a signal from the output of the generator 2 of a single pulse and the switch 3. With the arrival of the first clock pulse from the output of the generator 1 clock pulses, the i-th D-trkgg of register 4 receives the information from the (1-2) -th 1) -trigger 9.1-2 (, n) .. The first adder 5 modulo two forms1 -1 signal with the signal for the first D-flip-flop 9.1 register 4, and the second adder 6 modulo two for the second D-flip-flop 9.2 register 4. With the arrival of the following pulses, pseudo-random sequences are formed at the outputs of the D-TpHiger 9.1-9.m. , defined by a generating polynomial. In this case, the sequence formed at the output of the k-ro D flip-flop 9.k of register 4 is shifted relative to the sequence generated at the output of the (k-1) th D flip-flop 9.k-1 of register 4, by iN / 2j, where K is the period of a pseudo-random sequence,, mo Thus, in the next bits of the register 4, fps syryatc copies of the pseudo-random sequence shifted by N / 2, and with the help of delay element 7, the shift is carried out by N / 2. Summing up further these two copies of a pseudo, one of the random sequences on sumgator 8 modulo two, we get at its output a pseudo-random sequence with a doubled frequency. Claim 1. A pseudo-random sequence generator comprising a clock pulse generator, a register, first, second and third modulo-two adders, a delay element whose output is connected to the first input of a third modulo-two, the second input of which is connected to the first register output, the second and the third outputs of which are connected correspondingly to the first and second inputs of the second modulo-two adder, the output of which is connected to the first input of the register, the fourth and fifth outputs of which are connected to the corresponding One with the first and second inputs of the first modulo-two adder, characterized in that, in order to increase the reliability of operation, a single pulse generator and a switch are entered into it, the first output of which is connected to the second input of the register, the third input of which is connected to the output of the first modulo two torus sum, a quarter input of the register is connected to the second output of the switch, the first and second inputs of which are connected respectively to the outputs of the single pulse generator and the clock pulse generator, the sixth register output Inonii to the input of the delay element. /. 14 2, The generator according to claim 1, that is, that the register contains m D-flip-flops, the information input of the first of which is connected to the third input of the register, the first input of which is connected to the information input of the second D -trigger, informational input of i-ro D-flip-flop is connected to output (i-2) -ro D-flip-flop (, m), setup inputs m Dtriggers are connected to each other and to the second input of the register, the fourth input of which is connected to synchronization inputs ha D-flip-flops, the outputs (jl) -ro and j-ro of which are respectively the fourth and second outputs of the register (, m), the sixth and first outputs of which are connected respectively to the outputs of (kl) -ro and k-ro D-flip-flops (, m), the outputs of (m-1) -th and th-th of which are respectively fifth and the third register output.