SU1267427A1 - Interface for linking input-output channels with internal memory - Google Patents

Abstract

The invention relates to computing, in particular, to devices consisting of a number of input / output channels and a control device serving these channels in the time division mode, and the channels can be autonomous or embedded. The device allows generation of a modification code for data transfer operations. It also allows you to form a write mask to the RAM for operations that require not only increases, but also for operations with decreasing data addresses. The purpose of the invention is to expand the functionality by implementing the generation of a modification code for operations that require not only increasing, but also reducing the data address. The device contains a data switch, a byte switch, a mask generation unit, an address switch, .i operation code switch, a modulo-two adder block, a switch (L mask re-configuration, request priority block and modification code generation block. The specified set of blocks allows to achieve the goal of the invention. 1 Cp f-ly, 5 ill. u o :) 1 4 Yu

Description

The invention relates to a computing technique, in particular, to devices consisting of a number of input / output channels and a control device serving these channels in the time division mode, and the channels can be automatic or embedded.

The purpose of the invention is to expand the functionality by implementing the generation of a modification code for operations that require not only increasing, but also reducing the data address. .

FIG. Figure 1 shows the structural scheme of the proposed device for interconnecting input-output channels with random-access memory in FIG. 2 - functional block diagram of the formation of the modification code; in fig. 3 — functional scheme of mask location; in fig. 4 is a block diagram of a bit rearranging switch; FIG. 5 is a block diagram of modulo two adders.

The I / O channel interface with RAM (Fig. 1) contains a data switch 1, a byte number switch 2, a query priority block 3, a mask generation unit 4, an address switch 5, an operation code switch 6, an adders block 7 module two, switch 8 rearranging the mask, block 9 of the formation of the modification code.

FIG. channel 10 is designated, containing the data register 11, a 12 byte counter, a query block 13, a data address register 14, an operation code register 15. FIG. 1 denotes data inputs 16, 17 and byte numbers, respectively, request input 18, address input 9, operation code input 20, data output 21, request output 22, address output 23, mask output i24, modification code output 25.

The modification code generation unit 9 (FIG. 2) contains the first 26 and second 27 decoders, the priority encoder 28, the elements OR 29-35, the AND element 36.

The mask generation unit 4 (Fig. 3) contains a decoder 37, multiplexers 38-45 bits of the mask, elements OR 46-51.

The switch 8 mask rearrangement (Fig. 4) contains the switch 52.

67427i

Block 7 adders modulo two (Fig. 5) contains a group of adders 53 modulo two.

FIG. 2-5 designate communications 545 57 from the switch 2 to block 9 of the modification code generation, connection 5861 of the modification code generation unit 9, communication 62-67 of the decoder 37, communication 68-75 of the formation unit 4

10 masks, connections 76-78 from the switch

5 addresses to block 7 of modulo-two adders, links 79-81 from block 7 to block 4 of the mask and block 9 of the modification code.

15 Data switch 1 is designed to transmit data from the register 11 of the selected channel to the output 21 of the device data.

Switch 2 is designed to transfer the low-order bits from the 12 bytes counter of the selected channel to the mask generation unit 4 and the modification code generation unit 5. . The request priority unit 3 serves to determine the number of the most priority channel that requires the exchange of data 1-1 and the main memory (OP) by requests received from the request for data transmission unit I / O channels 13. This number is used to control the switches 1, 2, 5, 6. Block 3 also issues a request for data exchange with the OUT at the output

J, 22 device request.

The mask generation unit 4 is designed to obtain a recording mask in the PD by the lower data address addresses and the lower bits of the counter

Q 12 bytes for Read and Reverse read operations performed by I / O channels

The address switchboard 5 is intended for input to the output address 23 in the OP address

 data from the register 14 addresses of the selected channel.

The minor data address bits from switch 5 are used to form a mask and a modification code — in blocks 4 and 9, respectively.

The one-bit switch 6 of the operation code is designed to transfer the bit of the operation code from the register 15 of the channel's operation code to the corresponding 55 tWith inputs of the modulo-two adders 7 and the recompilation switch 8. The code of the operation code defines the operation performed by the channel as follows: O, Read operation or Write operation, 1, Reverse read operation.

Switches 1, 2, 5, 6 are made on multiplexers, the address inputs of which receive the number of the selected channel from block 3 of the priority of requests. This number sets the transmission through the multiplexer to the output of its information from the desired channel.

Modulo two adders block 7 serves to obtain the inverted lower-order data address bits for the Reverse read operation performed by the channel and transmit without inverting the data address through the lower-order block in the case of a Read operation or a Write operation

The device works as follows.

Before starting the operation requiring data exchange, the control information necessary for the exchange is loaded into channel 10. In the channels of the Unified System (EC) computer, such information is stored in the channel command word (CSC) in which the command code is set, which the peripheral device (PFC) must perform, the starting byte address of the RAM (RAM) from which the exchange should begin, the initial a counter value of that number of data bytes that is transmitted under the control of the current KSK.

In this case, the command code from the KSK sets the channel to perform one of the following three data transfer operations: Write - data output operation from the PD to the PFC when the address of the data byte during the operation increases and the value of the data counter is reduced by the number of bytes transmitted (modification code) ; Read - data entry operation from the PFC to the PD, in which the address of the data increases, and the value of the data counter decreases during the operation by the amount of the modification code; Inverse read is a data entry operation from a PFC to an OP, in which the address of the data and the value of the data counter in the operation are reduced by the modifying code. With the initial load of information from the KSK to channel 10, the code of the data transmission operation performed by the analog is placed in register 15 of the transaction, the starting data address is 267А27

in the register 14 data addresses, the initial value of the data counter - in the counter J2 bytes.

Simultaneously with the entry of the address 5 of the data in the register 14 addresses of the data,

younger bits of the data address, the byte number in the word is entered into the byte number counter (not shown). The number of such bits

to is determined by the length of the word OP, and with an 8-byte word OP, the number of these bits is three.

Then the data transfer begins. In operation Read data from PFC

15 byte by byte are received into the channel and directly with the interface, or through the data buffer in the channel are transmitted to the data register 1I. The data is placed in the 20I register of the II under the control of a byte number counter, the contents of which are increased by one after receiving the data byte, preparing the reception of the next byte. Register 11

25 has the size of the word exchange with the OP. By barely filling the last byte of register 11 or receiving the last byte of the array by block 13, a request for a request is generated. raschenie to OP. The request signal comes from the input 18 of the device in block 3 priority requests for data transfer. Elok 3 generates an exchange request signal, arriving at the output 22 of the device. By this signal

 The OD is prepared for data exchange, and in the case of embedded channels on it, the processor is also preparing for data exchange. Block 3 also generates the address of the highest priority channel that requested the data transfer. This address goes to the control inputs of the switches 1, 2, 5, 6. Information from the selected channel is transmitted to the switch outputs. Through the data switch 1, the data word from register 11 is output to the device output 21 in the PD. Through the switch 5, the addresses to the output 23 of the device in the RAM output are issued from register 14.

 addresses the address of the word to which the data should be written. Three junior bits of the data address are fed to the corresponding input of the block of modulo two adders,

55 Through a one-bit switch 6 of the operation code, the potential, formed from the contents of register 15 of the operation code, is supplied to the corresponding inputs of the block 7 and switch 8 of the reassembly. In this case, O means that the Read or Write operation is performed, 1 means the Reverse Read operation. For the operation Read, arriving in block 7 at the inputs of modulo two adders, the zero level specifies the transmission of the lower-order address bits via the connections 7678 to the input of the beaconing unit 4 and the input 9 of the modification code generation unit (link 79-81) without inverting . The arrival in block 8 of the control input of the switch 52, the left level, sets the transfer of the beacon formed by block 4 to the output 24 of the device mask without re-linking. (The highest mask bit received from block 4 by link 75 is transmitted as a bit (0) of a mask, the low bit mask obtained by link 68 is sent as a bit (7) of the mask). Through switch 2, four bits arrive at the inputs of blocks 4 and 9 via communications 54-57, displaying a counter value of 12 bytes. In communications 54-56, the lower bits of the data counter are issued (in communications 54, the least significant counter is issued). ON COMMUNICATION 57 is issued O in the event that all the other high bits of the data count are zero, and I is issued if, in the count bits; data, excluding the three least significant bits, there is at least one bit set to 1 Single signal on link 57, which means that the data count value on the channel is not less than 8 (-1000 combination). The data recorded in the AS is accompanied by a mask defining those bytes in the data word, which should replace the corresponding bytes of the word read from the OP. The mask size is determined by the number of bytes in the word, and for the considered device implementation example is equal to B. The write mask in the PD is generated by the mask generation unit 4 according to the low-order bits of the data address obtained via links 79-81 from block 7 and the value of bits data counts obtained by communications 54-57 from four-bit switch 2 A mask is formed at the outputs of the multiplexers 38-45 of the mask. From the multiplexer 38 to the link 68, a lower mask bit is issued (bit 7). From multiplexer 45 to link 75, the high bit mask is issued (bit 0). The low order bits of the data are transmitted through communications 79-81 to the address inputs of multiplexers 38-45 (the younger of the bits enters through the link 79, the oldest of the bits from the link 81). In this case, the transmission of information from the inputs selected by the supplied address combination to the outputs of the multiplexers is permitted. So, with a combination of 011 supplied to the address inputs A4, A2, A1 multiplexers, the outputs of the multiplexers 38-45 will be transmitted information from the inputs D, At the outputs of the multiplexers corresponding to the digits with numbers ;, smaller than the octal number t, the combination supplied to the address inputs A4. A2, A1, zeros are formed due to the fact that the O level is fed to the selected inputs of these multiplexers. The output of the multiplexer of discharge i is 1, because the selected input of this multiplexer is supplied with level 1. The unit in this bit of mask is due to that the data count before the data transfer can not be zero. At the outputs of multiplexers corresponding to bits with numbers greater than i, the values due to the data count are formed. Minor data count. (octal number j) is decrypted in block 4 of mask generation by decoder 37. Signals from outputs of decoder 37, corresponding to data counting from 2 to 7, are sent to elements OR 46-51. The same elements are given a signal from the link 57, corresponding to a data count greater than 7. The level of the unit appears at the outputs: the OR element 51 when the data count is greater than 1, the OR 50 element when the count is greater than 2, the OR element 49 when the score is more than 3, element OR 48 with counting more than 4, element OR 47 with counting more than 5, element OR 46 with counting more than 6. When counting data greater than 7, the unit levels appear at the outputs of all six elements OR 46-51 as well as at the input to the multiplexer 38 due to the presence of a signal on the connection 57. On the selected 7

The inputs of multiplexers corresponding to bits with numbers greater than i are given in the order of increasing numbers of bits, signals from the outputs of the OR 51, 50 elements, etc. respectively,

If j is less than the number of bits with numbers greater than i, then at the outputs of the j bits of the mask, starting with bit i, there appear units. When j is greater than or equal to the number of bits with numbers large i, units appear at the multiplexer outputs of all these mask bits. The mask obtained in block 4 is transmitted to the output 24 of the device without rearranging the bits.

Simultaneously with the acquisition of the mask by the block 9 of generating the modification code by the value of the lower bits of the data address obtained from block 7 and the value of the data count bits obtained from the switch 2, the modification code is generated. The modification code is issued from block 9 to the output 25 of the device and is used to modify the data address and byte count. This modification for embedded channels is usually performed in the processor, for autonomous channels it can be performed in channels

In block 9, the least significant bits of the data address from links 79-81 are fed to the information inputs of the decoder 26, the lower bits of the counting from the links 5456 are fed to the information inputs of the decoder 27. The control of the decoder 27 performs the count of the bill, which arrives on 57 With a count greater than or equal to 8, the signal from link 57 blocks the decoder 27 and the modification code is generated by the lower bits of the data address (by the signal from the output of the decoder 26). With the combination 111, the output D of the decoder 26 is excited on the connections x 81-79, the unit level is fed through the OR element 29 to the input D of the encoder 28. On the connections x 61-58, a modification code 0001 is generated. Similarly, when a combination 110 of the outputs of the element 36 and the encoder 28 / connection 61-58 is applied to the connection 81-79), code 0010 is formed, with combination 101 it is code 0011, with combination 100 it is code 0100, with combination 011 it is code 0101, with a combination of 010 - code 0110, with com 67427, 8

001 is the code 0111, with a combination of 000, the output D of the decoder 26 is excited and the modification code 1000 is generated. 5 When the counting is less than 8 (

cash on communication 58 zero), address. the data located on the word boundary (combination 000 on connections x 81-79), the modification code is generated based on the data count (on the signal of the excited output of the decoder 27 of the count). The combination 001 on the connection x 5654 causes the excitation of the output D, the decoder 27 and the supply: single

15 signals through the element OR 29 at the input D of the encoder 28. At links 69, 60, 59, 58, a code 0001 of the modification is generated. Similarly, when filing on communications 57-54 combinations 0010 on

The 20 outputs of the AND 36 element and the encoder 28 (communications 61-58 form the code 0010, with the PLO combination the UN code, with the combination 0100 the code 0100, with the combination 0101 the code 0101,

25 with a combination of 0110 - code 0110, with a combination of 0111, the output of a D is excited, the decoder 27 and a code of modification 0111 is generated.

30 With an invoice smaller than 8 and the data address is not on the word boundary at

elements OR 29-35 filed a single signal from one of the outputs of the address decoder 26 and a single signal from

35 one of the outputs of the decoder 27,. These single signals correspond to the receipt of a modification code, respectively, by data address or byte number.

40 Single signals can be sent to the two inputs of the encoder 28. Since the encoder 28 generates a code for a higher priority input, the smallest of the two possible codes (the code obtained at the data address, and the code received by the data account).

Modification code with links 58-61. is provided at device output 25.

Claims (2)

After the word is written to the SP, the data address is increased by the amount of the modification code, and the modified value of the data address is listed in the data address register 14. The value of the data count is also reduced by the value of the modification code, by which the new value of the I2 byte counter is formed, 9 In the data register 11, starting from the zero byte, the next word is formed. The appeal to the memory and the actions associated with it are repeated after; accumulation in register 11 of the data of each next word. If the array does not end at the word boundary, the last word is incomplete, and the corresponding mask contains zeros in one or more low-order bits. In the Record operation, when it is necessary to read from the OP the data word, block 13 generates a request signal for accessing Oil, coming from the input 18 of the device to block 3, the priority of requests. The device blocks in the Write operation work in the same way as in the Read operation. The mask applied by the device to output 24 is not used when reading from the OP. The modification code generated by the device at output 25, ka and for Read, serves to modify the data address and the data count. The data received in channel 0 from the PD, is sequentially byte-by-byte output to the PFC directly from the data register 11 or via the data buffer in the channel. Data output to the PFC may be performed under the control of a byte number counter (not shown) indicating the number of that byte in the word that is needed. to issue. After each byte output in the PFC, the contents of the byte number count are incremented by 1, preparing the output from the next byte. When the data register 11 is free, and the value of the 12-byte counter is not zero, the block 13 sends a request for data transmission to the next request for accessing the OP. In the case of the Reverse Reading operation, the difference between the operation of the device and its operation during the Reading operation is the inversion of the m1d bits of the address of the data before they are fed into blocks 4 and 9 and the reassembly of the bits generated by block 4 of the mask on the reshaping switch 8. These actions allow for the Reverse Read operation, which requires decreasing the data address, to form a mask in block 4 and the modification code 2710 in block 9, in the same way as for the Read operation. In block 7, the unit level coming from switch 6 The operation code for the inputs of modulators 53 modulo two sets the inversion of the lower address bits (links 76-78). The inverted address from block 7 via connections 79-81 B receives the mask generation block 4 and the modification code generation block 9. The mask bits, obtained in block 4 according to the principle outlined for the Read operation, are fed to the input of the recompilation switch 8. The level of the unit arriving at the control input of the switch52 specifies the rearrangement of the mask bits before it is issued to the device's mask 24. The lower mask bit from block 4 from link 68 is transmitted through switch 52 as the high bit (0) of the mask. Mask bits with links 69-74 are transmitted through switch 52 as respectively bits (1-6) masks. The highest mask bit from block 4 from link 75 is transmitted through switch 52 as the low bit mask. Simultaneously with the mask of the inverted junior address addresses, in block 9 of the generation of the modification code, the modification code obtained at the output 25 of the device is obtained. The modification code is then obtained in the same principle as for the operation Read, Claim 1. An apparatus for interfacing the I / O channels with the RAM, containing a data switch, a switch for the byte number and a mask generation unit. The information inputs of the switch data and switch byte numbers are connected respectively to the data input and output of the device byte number, data switch output is connected to the device data output, switch output byte number is connected to the first input of the form block unveiling a mask, characterized in that, in order to expand the functional. capabilities by implementing the generation of a modification code for operations that require not only increasing, but also reducing the data address. an address switch, an operation code switch, a modulo-two adder block, a mask remaking switch, a request priority block and a modification code generation block are entered into ftero, the information inputs of the address switch, the operation code switch and the query priority block are connected to the address input and the code input operation and input device requests, the output of the address switch is connected to the first input of the block of modulo two adders and connected to the address output of the device, the output of the operation code switch connected to the second input of the block of adders modulo two and to the control input of the switch of mask rearrangement, the output of which is connected to the mask output of the device, the information input of the switch of mask rearrangement is connected to the output of the mask generation unit, the second input of which is connected to the output of the block of adders modulo two and with the first input of the modifier code generation unit, the second input of which is connected to the output of the byte switch, the output of the modifier code generation unit is connected to the output of the modification code In this case, the output of the priority request number of the request priority block is connected to. the control inputs of the switch — the address, the switch of the operation code, the switch of the byte number, and the switch of the data; the request output of the request priority block is connected to the output of the request, the device. 2. The device according to claim 1, characterized in that, the modification code generation unit comprises two decoders, an AND element, seven OR elements and a priority encoder, the input of the first decoder is bit-wise connected to the first input of the block, the first bit of the second input the block is connected to the first input of the element I, the second input of which is connected to the first output of the first decoder, the remaining bits of the second input of the block are connected to the corresponding bits of the information input and the gate input of the second decoder, from the first to the seventh you the moves of which are connected respectively to the first inputs of the first to seventh OR elements, the second inputs of which are connected respectively to the second to the eighth outputs of the first decoder, the output of the AND element is connected to the first input of the priority encoder and connected to the first bit of the output of the block, the remaining bits of the block output connected to the corresponding bits of the output of the priority encoder, from the second to the eighth inputs of which are connected to the outputs, respectively, from the first to the seventh OR elements. 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