SU1265774A1 - Device for time checking of input-output operations - Google Patents

Description

The invention relates to computing and can be used to temporarily monitor input-output operations in computer input-output channels.

The purpose of the invention is to increase the completeness of the time control of I / O operations.

The drawing shows a diagram of the proposed device.

The device for time control of I / O operations contains counters 1-3, trigger 4, generator 5 pulses, element NOT 6, elements AND 7-1, elements OR 12 and 13, switch 14, first 15 and-16 second input buses, input 17 auto mode and exit 18.

The first input bus 15 contains the lines of the signals coming from the channel control unit: 19 - reset, 20 the Start I / O command completes, 21 - the command chain is completed, 22 is the microprogram signal, from which the unit is subtracted from the second counter 2, 23 - interrupt signal, 24 - firmware reset.

The second input bus 16 contains the signal lines coming from the interface control unit: 25 - initial sampling signal, 26 - UPR-A (subscriber control), 27 - zero to DMH-A (subscriber state).

The device works as follows.

The first input bus 15 is connected to the channel control unit, the second input bus 16 is connected to the interface control unit, the input 17 is connected to the engineer console, and the starter 18 is connected to the channel control unit. The switch 14 represents the multiplexer itself, the information inputs of which are connected to the outputs of certain bits of the third counter 3, and switching the address inputs by jumpers allows to receive counting pulses with different periods, for example 1, 3, 10, 30 s, etc. After the system has been reset (input bus 15 signal 19), counters 1 and 2 are reset, trigger 4 is reset. The zero state of the counter 2 blocks the passage of the counting pulses through the element 7 to the input of the counter 1.

Each I / O operation starts on the Start I / O command, and the line 20 of the input bus 15 is energized.

the peripheral device sends the zero initial status byte to the sample, then by coincidence of the signals 25-27 at the inputs of the element 10 the signal from its

output through the elements of AND 8 and OR 12 enters the input of counter 1 and resets it and the trigger 4. The signal from the output of the element And 8 is also fed to the input of counter 2, adding one. The contents of counter 2 become different from zero, and the signal from the output of the element OR 13 allows the passage of counting pulses through the element 7 to the input of counter 1. The latter begins to count the time interval allotted for the execution of the input-output operation.

A table in the control memory is used to control the I / O operation. In the table, each address of the peripheral device corresponds to a string, one bit of which is used to temporarily monitor I / O operations. The firmware implementing the Start I / O command, determining that a zero initial status byte has been received in the initial sample, sets this control bit to one.

If an I / O operation is performed using a chain of commands, then each time the initial sample in the chain is executed, the co-. mand, excited entrance 21 input pshny

5 15 and the signal from the output of the element And 10 through the elements And 9 and OR 12 executes the reset of counter 1 and trigger 4, after which counter 1 starts counting with zero.

0

The accomplishment of the I / O operation ends with the fact that the peripheral device sends the final state byte with the bit The device has finished.

 When the channel receives a status byte, an interrupt trigger is set in the channel control block, input 23 of the first input bus 15 is energized, and the signal from the output of the NOT element 6 blocks the passage of counting pulses to the input of counter 1. The signal at input 17 enables the passage of counting pulses to the counter 1 only in the automatic mode, if the switch of the operating mode is in the command or 1 co-ordinate position, the device is blocked, which is convenient during adjustment work.

The channel processing interrupt microprogram analyzes the control bit in the table for this peripheral device and, if installed, analyzes the device status and channel bytes. If it detects one of the device bits, Device Crash, Device Failure, Security Violation, Program Error, Channel Control Failure, Interface Control Failure, then it clears the control bit in the table and generates a signal at input 22 of input bus 15, through which one is subtracted from counter 2 . If one channel of I / O is running on a channel, then after subtracting 2 units from the counter, it is zeroed out, which blocks the passage of counting pulses to counter 1. If several channel I / O operations are running (maximum 255) on different peripheral devices, then their number is indicated in counter 2, since each time the next input / output operation is started, the state of counter 2 is increased by one. Every time one of the started I / O operations ends (an interrupt is processed for it), one is subtracted from the contents of counter 2.

IF for some reason, during the time allotted for performing an I / O operation, it is not finished, the overflow signal from the output of counter 1 sets the trigger%, the signal from the output of which in the channel control unit sets the request for microprogramming suspension. Next, the situation processing firmware is executed.

Two situations are possible.

A. The loaded channel hangs (the device logically connected to the channel did not produce any signal expected by the channel). In this case, the firmware sets the interface failure control, performs channel registration, selective reset on the interface, sets the interrupt trigger in the channel control block, from which the output through the NOT 6 element blocks the passage of counting pulses to the input of counter 1, reset the counter 1 and trigger 4, for which excites input 24 of input bus 15 and performs a return to the suspended firmware.

B. The channel is free. The firmware sets the channel load trigger and the interrupt trigger in the channel control block, resets counter 1 and trigger 4, for which it excites input 2D of the input bus 15 and eliminates the return to the suspended firmware.

In order to find a peripheral device for which the I / O operation has not been completed, the microprogram for interrupt processing scans the table in the control memory for the detection of a row with the control bit set. Having found a line in the table with the control bit set, it clears this bit, from the address of the line forms the address of the peripheral device5 for which the fault is filled, forms the corresponding device status byte, writes the channel status word and resets the interrupt trigger.

Claims (1)

Invention Formula A device for time control of I / O operations containing a trigger, first element AND first element OR, a pulse generator, the first counter whose overflow output is connected to a single trigger input whose output is a device output, zero trigger input connected to the output of the first OR element and with the reset input of the first counter, whose counting input is connected to the output of the first element AND, the first input of the first element OR is connected to the reset input of the device, characterized in that, in order to increase completeness in belt control I / O operations, it contains the second and third counters, the switch, the second element OR, the second, third, fourth and fifth elements AND, the element is NOT, the first input of the first element AND is connected to the output of the second element OR whose inputs are connected with the outputs of the second counter, input + of which is connected to the output of the second element AND, and to the second input of the first element OR, the third input of which is connected to the output of the third element AND, the first input of which is connected to the output of the fourth element AND, and with the first input $ 12657746 The house of the second element is And, the second input is connected to the output of the element NOT, which is connected to the input of the Start input of which is connected to the device input-output input, the input of the drive, the second input of which is connected to the second input of the input element , three entrances of the even-5th mode of the device, the third of the correct element And are connected to three inputs of the fifth element And connected to the outputs of the signs of the device, the input of the switch, information reset operations of the device connected to the inputs to second connected to the outputs with input -1 of the second counter, the third counter, the counting input of which is connected to the input of the device connected to the output of the device’s reset generator, the second input of the first pulses, the fourth input of the first element I connected to the output of the p element OR is connected to the input of the common element I, the first input of which the device is reset.