SU1265629A1 - Analogue-digital peak detector - Google Patents

Abstract

This invention relates to electrical measuring technology. The purpose of the invention is to increase the speed of the device. The detector contains an analog-to-digital converter 2, a memory block 3 and an analog comparator 5. The introduction of analog peak detector 1, digital comparator 4, single-oscillator 6, key 7 and the formation of new connections between the elements of the device allow included in its composition, to obtain high accuracy and ensure the speed of the device as a whole. 1 il. (L S th F sd od (S ko

Description

(54) ANALOG-DIGITAL PEAK DETECTOR '(57) The invention relates to an electrical measuring technique. The purpose of the invention is to increase the speed of the device. The detector contains an analog-to-digital converter 2, a memory unit 3, and an analog comparator 51. The introduction of an analog peak detector 1, a digital comparator 4, a single vibrator 6, a key 7, and the formation of new connections between the elements of the device allows obtaining low requirements for the parameters of the units included in its composition accuracy and ensure the performance of the device as a whole. 1 ill.

SU .. „126562>

The invention relates to electrical engineering,

The purpose of the invention is to increase the speed of the device.

The drawing shows a block diagram of an analog-to-digital peak detector.

The device contains an analog peak detector 1, the input of which is connected to the input bus, and the output through an analog-to-digital converter 2 is connected to the input of the memory unit 3 and the first input of the digital comparator 4, the output of block 3 is connected to the second input of the comparator 4 and the output bus of the device, analog a comparator 5, the first input of which is connected to the input 'bus, the second input - to the output of the detector 1, and the output - through a series-connected single-vibrator 6 and key 7 to the control input of the write permission block 3, the control input of the key 7 is connected It is connected to the output of the comparator 4, the reset inputs of the detector 1 and block 3 are connected to the Reset device bus.

An analog-digital peak detector operates as follows.

Before starting work, the detector 1 and the memory unit 3 are reset by a pulse from the Reset bus. At the output of the comparator 4 there is a signal Log. About when the value of the code at the output of the Converter 2 is less than or equal to the value of the code at the output of the memory unit 3 and the signal Log. 1 in the opposite case. Thus, in the initial state, a signal Log is generated at the output of the comparator 4. Oh, which closes the key 7.

With increasing voltage at the input of the analog peak detector ί, it simultaneously increases at its output. Converter 2 converts this voltage to digital binary code. In this case, the comparator 4 is activated, since the code from the output of the converter 2 exceeds the output code of the memory unit 3.

When the input signal passes through the maximum value, the i analog comparator 5 is triggered, since the voltage at its first input becomes less than the voltage at its second input, which remains almost unchanged and equal to the peak value of the input signal for a certain period of time. The single-vibrator 6 generates a pulse which, through the closed key 7, is fed to the recording permission input of the memory unit 3, thereby recording the code value from the output of the converter 2. After the recording is completed, the code values on the inputs of the comparator 4 become equal, which leads to its operation and opening the key

7. In this mode, the peak value of the input signal can be stored with constant accuracy for any length of time.

In the event that a new peak appears in the input signal, the amplitude of which is greater than the stored one, the analog-digital peak detector works similarly to that described, while the stored previous peak value of the signal is automatically erased from memory unit 3, and a new higher value is written instead.

In the event that one of the peak values of the input signal is followed by a peak of a larger amplitude, but after a time shorter than the pulse formation time by a single-shot 6, the latter is restarted, and the maximum value of the next peak and increasing in amplitude amplitude will be written into memory block 3 values. If the next peak of the signal is less than the previous one, the comparator 5 will not work, and the recording pulse will not be generated.

If after a long storage time, when the voltage at the output of the detector 1 drops to a value so small that the next peak of the input signal, the value of which is less than recorded in block 3 of the memory, triggers the comparator 5, the contents of the block 3 of the memory are not updated since key 7 is still open by the Log signal. About the output of the comparator 4.

The requirements for the blocks included in the analog-to-digital peak detector are low compared to the parameters provided by the analog-to-digital peak detector as a whole. So, the speed of converter 2 is selected in this case, based on the permissible error of changing the maximum value of the input voltage stored by analog peak detector 1, which allows the use of slow-acting accurate analog-to-digital converters3

File (ADC), for example, integrating type.

'The requirement for the storage time of analog peak detector 1 also turns out to be low, since this 5 time only depends on the conversion time of converter 2. This allows the use of a small capacitor in analog peak detector 1, which in turn allows one to obtain high speed and accuracy detector 1.

There are also low requirements for the accuracy of the formation of the time interval through which a write pulse is generated at the output of the one-shot 6, since the accuracy is mainly determined by the accuracy of the voltage storage of the detector ¹ rum 1. '

Thus, the proposed analog-to-digital peak detector makes it possible to obtain high accuracy and speed of the device as a whole with low requirements for the parameter 25 frames of the blocks included in it.

Claims (2)

The invention relates to electrical measuring equipment. The purpose of the invention is to increase the speed of the device. The drawing shows a block diagram of an analog-digital peak detector. The device includes an analog peak detector 1, the input of which is connected to the input bus, and the output is connected via analog-digital converter 2 to the input of memory block 3 and the first input of digital comparator 4, output of block 3 connected to the second input of the comparator 4 and the output bus of the device, analog comparator 5, the first input of which is connected to the input bus, the second input to the output of the detector 1, and the output via the connected one-shot vibrator 6 and key 7 to the pack the write enable input of block 3, the control input of key 7 is connected to the output of comparator 4, the reset inputs of the detector 1 and block 3 are connected to the Reset Device bus. Analog-digital peak detector works as follows. Before starting operation, detector 1 and memory block 3 are pulsed off from the Reset bus. The output of the comparator 4 is a signal Log, O when the code value at the output of the converter 2 is less than or equal to the code value at the output of memory block 3 and the signal Log. 1 in the opposite case. Thus, in the initial state at the output of the comparator 4, a signal Log is formed. O, which closes key 7. As the voltage increases at the input of the analog peak detector 1, it simultaneously increases at its output. Converter 2 converts this voltage into a digital binary code. This triggers comparator 4, since the code from the output of converter 2 exceeds the output code of memory block 3. When the input signal passes through the maximum value, the I analog comparator 5 is triggered, since the voltage on its first input becomes less than the voltage on its second input, which remains almost unchanged and equal to the peak value of the input signal during a certain time interval. One-shot 6 forms an impulse. which, via the closed key 7, is fed to the input of the write permission of the memory block 3, thereby recording the code value from the output of the converter 2. After the end of the recording, the value of the codes on the inputs of the para1 of the parator 4 becomes equal, which leads to its activation and opening of the key 7. In this mode, the peak value of the input signal can be stored with constant accuracy for a long time, In the input signal a new peak appears, the amplitude of which is greater than the memorized, the analog-digital peak detector works in the same way as described, the stored previous value of the signal peak is automatically erased from memory block 3, and instead of it records with new greater value. If one peak of the input signal is followed by a peak of greater amplitude, but after a time shorter than the pulse formation time by the single vibrator 6, the latter is restarted, and the value of the maximum of successive and increasing amplitude will be recorded in memory block 3 peak values. If the next signal peak is less than the previous one, the comparator 5 will not work, and the write pulse will not be generated. In the event that after a long storage period, when the voltage at the output of detector 1 drops to a value so small that the next peak of the current signal, the value of which is less than that recorded in memory block 3, results in the comparator 5 triggering T does not occur, since the key 7 is still open by the Log signal. A with comparator 4 output. The requirements imposed on the blocks included in the analog-digital peak detector are low compared with the parameters provided by the analog-digital peak detector as a whole. Thus, the speed of converter 2 is selected in this case, based on the allowable change error of the maximum input voltage stored by the analog peak detector 1, which allows the use of slow-acting analog-to-digital converters (ADC), for example, of an integrating type. The storage time requirement of analog peak detector 1 also turns out to be low, since this time depends only on the conversion time of converter 2. This allows the use of a small capacitor in the analog peak detector 1, which in turn allows a high response rate and the accuracy of the detector 1. The accuracy of the formation of the time interval through which a write pulse is formed at the output of the one-shot 6 is also low, since the accuracy is mainly determined by the storage accuracy April voltage rum 1. Thus, the proposed analogous th digital peak detector allows low x requirements to the parameters of blocks included within its structure, to obtain a high accuracy and speed of the whole device. Analog-to-digital peak detector containing an analog-to-digital converter, the output of which is connected to the input of a memory unit whose output is connected to the output bus and the reset input to the bus Reset detector, and an analog comparator, the first input of which is connected to the input bus a detector, characterized in that, in order to increase speed, an analog peak detector, a digital comparator, a single vibrator and a key are inserted in it, the analog peak detector input connected to the detector input bus, and the output - to the input of the analog-digital converter and the second input of the analog comparator, the first input of the digital comparator is connected to the output of the analog-digital converter, the second input - to the output of the memory unit, and the output - to the control input of the key, the output of the analog comparator is connected to the control to the input of the memory unit through a serially connected one-shot and a key.