SU1257840A2 - Modulo 4n counter - Google Patents

Description

The invention relates to computing and automation and can be used for pulse counting and is an improvement of the invention in accordance with the author. St. No. 523529.

The aim of the invention is to increase the speed of the modulo 4N counter by reducing the large load (2N- | -1) experienced by the outputs of the switching trigger, which is a limited quantity. When the logic elements of the switching trigger are powerful enough and provide large static currents (which allows the logic element to have a large load capacity), a significant capacitance to the substrate due to the large output bus branching will dramatically reduce the counter speed with increasing N.

The figure shows a modulo 4N counter circuit for the case when.

The counter modulo 4N (, 2,3 ...) contains 2N-J - 1 RS-flip-flops, executed on AND-OR-NOT gates. Switching RS flip-flop 1 contains 2N unit write gates, 2N zero record gates and two memory gates, one in each arm. The remaining RS-flip-flops form a push-pull shift register 2 with the main and auxiliary triggers, in which the unit output of the last RS-trngger is connected to the first input of the zero write valve of the first RS-trigger, and the zero output of the last RS-trigger is connected to the first input of the gate valve units of the first RS flip-flop. Each RS-register trigger 2 has one recording valve

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units and zero. The counting input 3 of the device is connected to the inputs of the memory gates of the switching trigger and to the second inputs of the zero recording gates and units of the RS flip-flops of the shift register.

The third inputs of the zero recording gates and the units of printed RS flip-flops of register 2 are connected to one of the switching trigger outputs, and the third inputs of the zero write gates and the even-numbered RS flip-flops of register 2 are connected to another output of the switching RS flip-flop, the inverse output of the last RS flip-flop the push-pull shift register is connected to the inputs of the memory gates of the switching RS-flip-flop and the inputs of the zero-write gates and the units of the RS-flip-flops of the push-pull shifting register of the second counter, performed in the same way as the first.

Counter modulo 4H works as follows.

When a counting pulse arrives, only one RS-trigger of register 2 is switched, the choice of which is determined by the state of the previous RS-flip-flop and switching RS-flip-flop.

After the end of the counting pulse, the switching trigger switches to the new state, in accordance with the new state of register 2, by intercepting the state.

The counter performs the count modulo 4N in a cyclic code with an increase from 0 to 2N and with a subsequent decrease from 2N to O the number of units in the image of numbers from O to 4N.

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five

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Claims (1)

COUNTER FOR 4 N MODULE by author. St. No. 523529, characterized in that, in order to improve performance when N is a complex number, the inverse output of the last RS-trigger of the push-pull shift register is connected to the inputs of the memory valves of the switching RS-trigger and to the inputs of the write gates of zero and one of the RS-triggers of the push-pull shift register of the second same counter. 1 _g - G - \ / J d ________ VI '___ ϊ _____ I lich LEE la IΛ I g I Г | 7 “Ιλ 'i rr4 z w lei / hh ης