SU1256226A1 - Phase synchronization device - Google Patents

Abstract

The invention relates to radio engineering. The capture bandwidth is extended. The device contains a digital phase detector 1 consisting of a multiplier 24 and an ADC 25, a digital lowpass filter 2, two adders 3 and 4, a shift register (PC) 5, a reference generator 7, a driver 8 pulses, a unit 9 for adding and reading pulses and frequency divider 10 (DCH). To achieve the goal, a PC 6, two PM 11 and 12, a distributor of 13 pulses, four elements AND 14-17, four elements AND-NOT 18-21 and two elements OR 22 and 23 are entered into the device. At the same time, the phase shift of the output signal occurs after the account of the change in the number of pulses at the output of the frequency module tO by the block 9 of the addition and subtraction of pulses. Adding or erasing one pulse abruptly changes the phase of the output signal by i2 ir / D, where D is the frequency factor of the PM 10. 1 sludge. S (l

Description

one

The invention relates to radio engineering and can be used for phase synchronization in receivers of discrete information.

The aim of the invention is to expand the phase locking bandwidth.

The drawing shows a structural electrical circuit of the phase synchronization device.

The phase synchronization device contains a digital phase detector 1, a digital low-pass filter 2, first and second adders 3 and 4, shift register 5, additional shift register 6, reference generator 7, pulse shaper 8, pulse addition-9 unit, frequency divider 10 , the first and second additional frequencies 11 and 12 frequencies, the distributor 13 pulses, the first 14, the second 15, the third 16 and the fourth 17 elements And, the first 18, the second 19, the third 20 and the fourth 21 elements AND-NOT, the first 22 and The second 23 elements are OR, and the digital phase detector with Holds the multiplier 24 and the analog-to-digital converter (ADC) 25.

The phase synchronization device operates as follows.

The signal input of the digital phase detector 1 receives an input signal, the second input receives a signal from the output of frequency divider 10. The digital phase detector 1 can be made in the form of a serially connected multiplier 24 and A / D converter 25. The error signal taken from the output of the multiplier 24 is converted into a code through the 1 / f time element. The sampling frequency fj is selected from the condition fа 2F, where Hz is the frequency offset,

The phase error code is fed to a digital lowpass filter 2 and a second adder 4. Digital lowpass filter 2 performs the function of a digital integrator, and is proportional to the branch formed by connecting the output bits of the ADC 25 to the second adder 4, the ADC code 25 and the digital filter 2 code the lower frequencies control the frequency of the output signal taken from the frequency divider 10, Upon arrival at the clock input

ten

562262

register 5 shift or additional register 6 shift pulses at time t, pT (; t pT, where T (- period of clock pulses

5 shift register 5, Tj is the clock period of the additional shift register 6, the binary code of the digital filter 2 of the lower frequencies is added to the contents of the additional shift register 6, and the binary code of the ADC 25 is added to the contents of the shift register 5. the first 3 and second 4 transfer signal adders, if

5 code direct, or loan, if the code is additional, allows the correction phase of the output signal.

With the direct code from the digital low-pass filter 2 at the input of the third element I 16 there is 1, when the transfer signal appears on. the output p of the first adder 3 is allowed to pass a clock pulse from the output of the second additional divider 12 frequency through

the third element AND 16 to the second input of the first element OR 22, on the first input of which O is present (since fti and fr are shifted one relative to the other), the output pulses of the first element OR 22 arrive at the input of the addition unit 9 - pulse subtraction and abruptly change output phase

“2 35a

With the additional code from the digital filter 2 low frequencies at the input of the third element And 16 there

O, and at its output - also O. At the third input of the fourth element I 17 there is 1, When a loan (O) appears at the output P of the first Adder 3, the clock pulse passes from the second of the additional divider 12 frequencies through a quarter the element AND 17 to the input of the second element OR 23, on the other input of which O is present. The output pulses of the second element OR 23 are fed to the control input of the block 9 to add JJ-deduction of pulses and abruptly change the phase

2t

output signal to

D

The second arm, which includes the second adder 4, the shift register 5, the first 14 and the second 15 elements And and Per3

18 and the second 19 second IS-NOT elements work similarly.

The phase shift of the output signal occurs due to the change in the number of pulses at the output of the frequency divider 10 by the addition-subtraction block 9. Adding or erasing one pulse abruptly changes the phase of the output signal to 21

t person

D

where D is the coefficient

divide frequency divider 10,

From the outputs of the first 11 and second 12 frequency dividers short clock pulses come in frequency

 and f to the input of the shift register 5 and the shift register 6 additional, respectively. Additional dividers 11 and 12 of the frequency are connected to different outputs of the distributor 13 pulses, so that the clock pulses are at a frequency f, and do not coincide in time.

The slope of the characteristic for, taken from the A / D converter 25, is determined by the choice of the clock frequency f.

S,

JiL D

The slope of the characteristic for the signal taken from the output of the digital low-pass filter 2 is determined by the choice of the clock frequency

h - / 71 2 - D

By setting the slope of the control S, and 82, the desired noise band of the device can be obtained.

Claims (1)

Invention Formula A phase synchronization device containing a digital phase detector, whose outputs through a digital low-pass filter are connected to the first inputs of the first adder, a reference generator whose output is through a serially connected pulse generator, an addition-subtraction unit. And a frequency divider connected to one of the inputs of a digital phase detector Which is the output of the device, the signal input of which is another input of the digital phase and reference detector, as well as the second 562264 an adder, whose outputs through the shift register are connected to one of the inputs of the second adder, is due to the fact that, with the 5 purpose of expanding the capture band of the phase synchronization, an additional shift register, AND-NOT elements, AND elements, and OR elements , additional dividers hour10 tots and pulse distributor. the outputs of the digital phase detector are connected to other inputs of the second adder, the transfer output of which is connected to the first to the input of the first element Both directly and to the first input of the second - element AND through the first element NAND, the output of the digit bit of the digital phase detector is connected via The second element AND-NOT to the second input of the first element AND and directly to the second input of the second element AND, the third input of which is combined with the third input of the first element AND and the clock input of the shift register and connected to the output of the first additional frequency divider, the outputs of the first and second elements And, respectively, through the first and second elements OR are connected to the corresponding inputs of the unit for adding and subtracting pulses, the outputs of the first adder through an additional shift register are connected to the second inputs of the first ummatora whose carry output is connected to first inputs of the third AND gate, and directly to a first input of the fourth AND gate through the third element NAND, the output of the digit bit of the digital lowpass filter is connected via the fourth element NAND to the second input of the third element AND and directly to the second input of the fourth element AND, the third input of which is combined with the third input of the third element AND and with the clock the input of the additional shift register and connected to the output of the second additional frequency divider, the outputs of the third and fourth elements AND are connected respectively to the second strokes of the first and second elements OR, and the output of the driver and Ls is connected to the inputs of the first second additional dividers of the frequency indicator.