SU1252955A2 - Device for checking adequacy of information transmission by quasiternary code - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to extend the functionality by detecting errors in the CM1 transmission code. The device contains a rectifier 1, three elements SHSh 2-4, a counter 5, an executor of 6 clock frequency, a shaper of 7 clock pulses, two elements HE 8 and 9, two triggers 10 and II, four elements AND 12-15, a logic unit (LB ) 16, consisting of Two counters (C) 17 and 18, five elements AND 19-23, two elements NOT 24 and 25, three triggers 26-28, and element OR 29 In case of violation in the CM code, 1 order of alternation of the combination 00 and II at output C 17 and 18, an error pulse appears. With the correct alternation of the combinations, C 17 and 18 are reset to the zero state. According to the intensity of the occurrence of error signals, it is possible to judge the state of the communication channel and control the reliability of information transmission. 1 il. t nm-s AHI CMI to

Description

The invention relates to radio engineering, can be used to control the accuracy of information transmission by a quasi-trivial code and is an improvement of the invention according to the author. No. 906011.

The purpose of the invention is to extend the functionality by detecting errors in the CMI transmission code.

The drawing shows a structural electrical circuit of the proposed device.

A device for controlling the reliability of information transmission by a quasi-trod code contains rectifier 1, first 2, second 3 and third 4 OR, counter 5, clock frequency 6, shaper 7 clock pulses, first 8 and second 9 HE, first 10 and the second And the triggers, the first 12, the second 13, the third 14 and the fourth 15 And elements, the logical unit 16, consisting of the first 17 and second 18 counters, the first 19, second 20, third 21, fourth 22 and fifth 23 And elements, the first 24 and second 25 elements are NOT, the first 26, the second 27 and third are 28 trigger moat and OR 29.

The device works as follows. I

The bipolar signals of the AMI and NDV-3 codes of the CM1 code, passed through rectifier 1, where the bipolar signals are converted into two sequences of unipolar pulses, and the unipolar signals of the CM1 code do not change, are sent for analysis to the logical part of the device of two identical parts. The first shaft, the logical part consisting of the first element OR 2, the first element NO 8, the first trigger 10, the first 12 and the second I3 elements AND, detects bipolarity violations in the signal transmitted by the quasi-trivial AMI code. At the output of the second element OR 3, a (k-l) pulse appears on a K sequence of pulses of the same polarity. The second logical part, consisting of the second element OR 3, the second element NOT 9, the second trigger 11, the third 14 and the fourth 13 elements AND, together with the third element OR 4 reveals signal violations in the NDV-3 code. On

The pulses of the same polarity at the first input of the device at the output of the third element I.PI 4 result in (k-2) pulses corresponding to the number of bipolar violations in the signal transmitted by the NDV-3 code. In a signal with a linear NDV-3 code, two pulses of the same polarity can follow one after another, and therefore the third

such an impulse will be a mistake

With the help of serially connected clock selector 6, clock generator 7 and counter 5 errors are detected

which do not correspond to the second condition for the NDV-3 code, namely, the appearance of a sequence at the input of the device with the number of the following subsets of zeros more than three. At the exit

the counter 5, the second output of the device will receive a pulse signaling the appearance of four zeros of the order, which is a sign of an error for the NDV-3 code. Impulses from the output

counter 5 is fed to the auxiliary input of the third IL 4 element, thereby increasing the number of error signals detected by the violation of alternating polarities of pulses.

To detect errors in the CM1 code, it is necessary to detect violations of the alternation of combinations 00 and 11 and the occurrence of forbidden combinations 10

on the clock transmission interval, what happens as follows. I

Information signals of the CM1 code from the output of the first element OR 2 are fed to the input of the first trigger 26

logic block 16 and a clock frequency to the input of the drive 6, in which in this case the double clock frequency contained in the GM1 signal is allocated. Double clock pulses

the frequency from the output of the imaging unit 7 clock pulses go to the second inputs of the second 27 and third 28 flip-flops, logic block 16, as well as to the input of the divider into two, as

which uses the first trigger 26, from the output of which the clock pulses arrive at the first 19, second 20, third 21 and fourth 22 elements of the logical block 16. From the outputs of the second 27 and third 28 triggers, the information signal is transmitted in parallel code to the first 19 and second 20 elements I. The appearance of a pulse at the output of the fifth element And 23 indicates the occurrence of a forbidden combination of 10 on the clock transmission interval. If the CMI code on the order of alternation of combinations 00 and 11 is disturbed, an error pulse will appear at the output of the first 17 or second 18 counter (capacity 2). With the correct alternation of combinations, the first and second counters will be reset to the zero state. Thus, at the output of the element OR 29 logical block 16, i.e. on the third output of the CMI device, they will be in

There are error pulses B in case of interlacing of combinations 00 and 11 and in the case of the occurrence of combinations 10 forbidden for the CM1 code on the clock transmission interval.

According to the intensity of the occurrence of error signals at the corresponding output of the device, it is possible to judge the state of the communication channel and control the reliability of information transmission.

The proposed device detects the overwhelming majority of errors in the transmission of information in the AMI, NDV-3 and CM1 codes and satisfies the requirements imposed on control devices without interruption of communication.

Claims (1)

Invention Formula and A device for controlling the reliability of information transmission with a semicircle code auth.St. No. 9060P, characterized in that, jc the purpose of expanding the functionality by detecting errors in the CM1 transmission code, a logic block is entered into it, the first and second inputs of which are connected by the corresponding editor A. Kozoriz Compiled by E. Golub Techred I. Veres Order 4632/58 Circulation 624 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, Projecto st., 4 0 five 0 five 0 five with the output of the clock pulses and the output of the first element OR, and the logic unit is made in the form of three triggers, five AND elements, two counters NOT, two counters and the OR element, the output of the first trigger is connected to the first inputs of the first, second, third, third and fourth elements And, the output of the second trigger is connected to the second input of the first element And to the first input of the third trigger, the output of which is connected to the second input of the second element And, the output of which is connected to the second input of the third element And, input n The first element is NOT and to the first input of the fifth element AND, the second input of which is connected to the output of the second element NOT and to the second input of the fourth element AND, the third input of which is connected to the output of the first element NOT, the input of the second element is NOT connected to the output of the first element AND the third input of the third element And, the output of which is connected to the information input of the first counter and to the Reset input of the second counter, the output of the fourth element And is connected to the information input of the second counter and to the Reset input of the first counter, outputs n The first and second counters and the fifth element And are connected respectively to the first, second and third inputs of the OR element, the output of which is the output of the logic unit and, accordingly, the third output of the device, the combined inputs of the first and second triggers and the second input of the third trigger block, the second input of which is the second input of the second trigger. Proofreader S. Shekmar