SU1249562A1 - System for transmission of information from mobile object - Google Patents

Abstract

The invention relates to data transmission systems from mobile objects and can be used in automated systems * of dispersion control of urban transport. The aim of the invention is to increase the reliability of the transmitted information. To achieve this goal, a device for transmitting information from a mobile object, comprising a transceiver connected to an antenna, the output of which is connected via a pulse shaper to the inputs of the first and second triggers and to the first input of the counter block, the output of the second trigger is connected to the first input of the transceiver, the third trigger , AND, OR, AND-NOT elements and a delay element, AND-NOT elements, connected to a code converter and a pulse distributor, are entered; a code converter is executed on a memory block, a decoder and multiplexer. The device provides for the possibility of serial control of information at the control point and makes it possible to eliminate possible operator errors. f-ly. 3 il. (L

Description

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O5 The invention relates to data transmission systems from mobile objects, in particular, to devices for transmitting discrete information from the rolling stock of urban passenger transport (bus, trolleybus, tram, taxi), and can be used in automated dispatching systems for urban passenger transport. The purpose of the invention is to increase the accuracy of the transmitted information. In Fig. 1, a functional diagram of the device is shown; Fig. 2 is a code conversion circuit; Fig. 3 is a block diagram of a memory block; FIG. 4 shows a time diagram of the device operation. The device for transmitting information from a moving object contains (smofig 1) transceiver 1, control generator 2, pulse generator 3, first and second triggers 4 and 5, and a block of counters. 6, the delay element 7, the pulse generator 8, the input 9 of the distributor 10 pulses, the converter code 11, the output 12 of the code converter, the input 13 of the pulse distributor, the output 14 of the code converter, the input 15 of the pulse distributor, the input 16 of the pulse distributor, the first element I- NOT 17, element 18, the second element IS 19, pulse output 10 of the pulse distributor 10, the third trigger 21s output 22 of the code converter, the third and fourth elements of the IS 23 and 24, outputs 25, 26 and 27 of the code converter, element OR 28, the output 29 of the distributor 1-0 pulses, the distributor 1 0 pulses contains element AND 30, elements AND-NOT 31-33. The block of counters 6 contains counters 34,35 converter code 11 (see Fig.2) contains a memory block 36, a decoder 37 and a multiplexer 38. The memory block 36 (simofiGoZ) contains an electromechanical register 39 and multiplexer 40 The device works as follows the initial state, the device installed on the vehicle is in standby mode. The transmitter of the control point periodically sends a signal to record .podOB. When the vehicle passes in the zone of the antenna of the control point, transceiver 1 receives This signal sends it to the pulse driver 3, which converts the received signal in the video pulse. The request pulse comes from the output of the pulse generator 3 to the first inputs of trigger 4, trigger 5, the control input of the counter block 6 and through the OR element 28 to the second input of trigger 21 In this case, trigger 4 and trigger 5 are set to state 1, trigger 21 is set to state O, and counters 34 and 35 are set to zero state. The request pulse duration is sufficient to eliminate the effect of transients when installing circuits in the initial state and is about 10 ms. When a signal of a logical unit appears at the output of the trigger 5, the generator 8 is started, the clock pulses from the output of the second are fed to the counting input of the counter 34, to the input 9 of the distributor 10 pulses and to the second inputs of the AND elements -NO 23 and 24. The formation of the sync pulse at the beginning of the information telegram begins (smofiHo4). Throughout the entire time of the formation of the sync pulse, the trigger 4 is in the Go state. In this case, at its inverse output, a logical signal the zero arriving at the input of the pulse distributor 10, the first input of the element AND-NOT 17 and the first input of the element AND 18. The presence of a logical zero signal at least at one input of the element AND-HE 17 ensures the formation of its signal and, therefore, at the second input of the controlled generator 2 of the signal of the logical unit. The presence of a logical zero signal at least at one input of an element And 18, ensures the formation at its output, and hence at the first input of a controlled oscillator 2, a signal of a logical zero When it appears at the first input of a controlled oscillator 2. signal of the logical zero, and at the second input of the signal of the logical unit, at its output a signal is generated with a frequency of, for example, 60 kHz, corresponding to the code message (see Fig. 4). This signal arrives at transceiver I, which transmits it to the control point. The formation of a sync pulse ends after the arrival of the eighth clock

a pulse to the counting input of the counter 34 In this case, the trailing edge of the eighth clock pulse sets the counter 34 to the state 000, after which the least significant bit of the counter 35 is set to the state of the logical unit. The code combination from the outputs of the bits of the counter 34 is fed to the inputs of the decoder 37 (see FIG. 2), the first output of which (output 26 of the code converter P) appears a signal that sets the trigger 4 to the state O On the inverse output of the trigger 4 is a signal of a logical unit, which gives permission for the passage of pulses from generator 8 through element 30, Operational information about the vehicle is stored in memory block 36. This information is a binary-decimal code, each bit of which consists of four binary bits The operational information is entered into the memory unit 36 by the operator using an electromechanical register 39. Each binary-decimal bit transferred to the memory unit 36 is transmitted as follows. First, information bits of the binary bit are transmitted. Then, the required test symbol and a stop pulse (see Fig. 4), generated by the circuit, are transmitted. The transmission of each binary-decimal bit stored in memory block 36 is controlled by the counter 34 and the code converter 11. The counter 34 is changed. Its status is determined by the negative edge of each clock pulse passing to its counting input. Depending on the code combination, the following signals are formed at the outputs of the counter 34 at the outputs of the 1I code converter: output 14 is a signal of a logical unit (except for the states of the counter 34 100, 10 110 and 111), the output 22 is a signal of a logical unit (except for the states of the counter 34 PO and 111), the output 25 is a signal of a logical zero (except the state of the counter 34 100), the output 26 - a signal of logical zero (except for the state of the counter), at output 27 - a signal of a logical unit (except for

counter 34 111), and on the start of 1, the signal is a logical zero (except for a state of 34.000, 001) 010

011, when installed in which the output 12 generates logical signals corresponding to the discharge information code.

Thus, the transfer of each

the binary-decimal bit of information is carried out upon the arrival at the counting input of the counter 34 from the pulse generator of eight-pulse pulses. In this case, the transmission of information symbols is carried out at the time of arrival of the first four clock pulses, the generation and transmission of the check symbol at the time of arrival of the fifth clock pulse, and

pulse formation and transmission Stop is carried out in the interval between the falling edges of the sixth and eighth clock pulses.

The formation of the information send starts when the counter 34 is set to the state 000 and the low-order bit of the counter 35 is set to the state of the logical unit. The code combination from the output of the counter 35 goes to the address inputs of the multiplexer 40 (mofiGoZ). At the output of the multiplexer 40 and, accordingly, at the output of the memory block 36 according to the VITS four-bit binary code of the first binary-decimal digit of the code entered in the electromechanical register 39 o The code combination of the counter 34 000 is fed to the address inputs of the multiplexer 38 (.cm c, fig 2) provides the appearance at its output (output 12 of the code converter 11) of the first binary code bit appearing at the output of memory block 36, Sequential reading of the binary code bit from the output of the memory block 36 and the formation at the output of the controlled generator 2 of the corresponding signals occurs until the counter at the counting input of the counter 34 and the input 9 of the pulse distributor 10 of the trailing edge of the fourth (after the pulse has been formed) clock pulse. Conversion of a parallel code of each binary-decimal bit, sequentially appearing on the outputs of the memory block 36, into a sequential code is carried out using a multiplexer 38 in accordance with the code combinations from the output of the counter 34 supplied to its address inputs. Binary binary The code of the first binary-decimal discharge is supplied from the output 12 of the converter of the code 11 to the input 13 of the pulse distributor 10 (inputs of the AND-NE elements 31 and 33), which distributes the signals of logical units and zeros of the samples This is done in the following way. Since trigger 4 after the end of the formation of the sync pulse goes to state O, its inverse output, and therefore, at the first input of the AND element 30 (input 16 of the pulse distributor 10), the first input of the AND 18 element and the first input of the NAND 17 element forms a signal of the logical unit. When a multiplexer 38 (code converter 11 output 12) appears at the time a counter 34 is installed in a state 000, for example, a signal of a logical unit of a code combination, this signal enters through the distributor input 13:; pulses 10 at the input of the NAND element 33 and the second input element AND-NOT 31. When the clock pulse arrives from the pulse generator 8 to the second input of the element 30 (input 9 of the pulse distributor 10), at its output for the duration of the clock pulse there are signals of a logical unit supplied to the first inputs IENTs 31 and 32, The second input of the element AND-NOT 32 is supplied with a logical zero signal generated at the input of the HE element 33, and the third input is fed with a logical unit signal coming from the output 14 of the code converter 11 to the input 15 of the pulse distributor 10 Thanks to the presence of the signals of a logical unit at both inputs of the AND-31 elements at its output (output 20 of the pulse distributor 10), a signal of a logical zero is generated. At the same time, at the output of the NAND 32 element (the output 29 of the pulse distributor 10) a signal of the logical unit is formed, since at its second input there is a signal of the logical zero. Thus, when the pulse distributor 10 signal of the logical unit of the read code arrives at the input 13 124 2, the logical zero signal will be present at the output of the pulse distributor 10 for the duration of the clock pulse, and a logical unit signal at the output 29 of the pulse distributor 10. Due to the presence of a logical zero signal (coming from the output of the pulse distributor 10), a logical unit signal is generated at the first input of the NAND element 19 at its output and, accordingly, at the second input of the AND 18 element. Since the first input of the AND 18 element is present the output of the trigger 4, the signal of the logical unit, at the output of the element 18 and, respectively, at the first input of the controlled oscillator 2 generates; logical unit signal. At the same time, the signal of a logical unit from the output of flip-flop 4 arrives at the first input of the NAND element 7. At the second input of the NAND element 17, a signal of the logical unit is also generated, since the logical zero signal present at the output 25 of the code 11 converter is input NOT 24, at the output of which and, respectively, at the second input of the element AND-NOT 17 a signal of a logical unit is formed. The signal of a logical unit arrives at the third input of the NAND 17 element from the output 29 of the pulse distributor 10. Thanks to the presence of a logical unit signal at all inputs of the AND 17 element at its output and, accordingly, at the second input of the controlled generator 2 logical zero. When a signal of a logical unit appears at the first input of the controlled generator 2, and a logical zero signal at the second input, a signal with a frequency (for example 63 kHz) corresponding to code 1 in channel 1 is generated at its output (see, Fig 4) . At the end of the first (after forming the clock pulse) clock pulse coming from the output of the pulse generator 8 to the input 9 of the pulse distributor 10 and the second inputs of the AND-HEY elements 23 and 24 and the counting input of the counter 34, a pause is formed between the bursts. In this case, the counter 34 enters the state. During the pause between the clock pulses at the input of the element 30 (logical zero signal), a logical zero signal is generated at its output, applied to the first inputs AND-NOT 31 and 32. As a result, in the absence of clock pulses (during pauses) at outputs 20 and 29 of the pulse distributor 10, signals of a logical unit will be generated. At the same time, the signals of the logical unit will also be generated at the outputs of the AND-HEY elements 23 and 24 and, respectively, at the third input of the IS-HE 19 and the second input of the IS-NOT 17, since the second inputs of the IS-NE 23 and 24 signal logical zero from the output of the pulse generator 8, the first input of the element AND-NOT 17 receives the signal of the logical unit from the output of the trigger 4, and the third input - from the output 29 of the pulse distributor 10, due to the presence of the signal of the logical unit at all inputs of the element AND-17 at its output and respectively at the second control input 2 a signaling logical zero generator is generated. This signal will be present at the second input of the controlled generator 2 in the process of forming pauses between any spaces. At the same time, the signal of a logical unit arriving from the output 20 of the pulse distributor 10 o will be present at the first input of the NANDI element. The signal of the logical unit arrives at the second input of the NI 19 element from the output 22 of the code converter 11, where it is present all states of the counter 34, except for the states 110 and 111. Thus, all inputs of the NAND 19 element will contain signals of a logical unit, as a result of which, at the output of the element 18 and the corresponding input, the signal 18 zero o at on If the signal of the logical zero at the inputs of the element 18 is at its output and, accordingly, the signal of the logical generator 2 is generated at the first input of the controlled oscillator 2, since both inputs of the controlled oscillator 2 contain signals of the logical zero 12 8 a pause is formed after the transmission of the first information impulse. Similarly, pauses are formed between other parcels, as well as the transmission of the synpause after the end of the pulse, each eight pulses are received in counting The input of the counter 34, from the generator 8, the state of the counter 35 changes. At the output of the multiplexer 40, the next interrogated binary-decimal information bit of the code stored in the electromechanical register 39 appears. After the transfer of the last bit of the transmitted information telegram code is completed from the output of the last bit of the counter 35, a delay reset signal 5 is applied through the delay element 7, see FIG. 1. When the trigger 5 is set to zero, the signal from the trigger 5 output locks the generator 8 and switches the transceiver 1 to Receive. The delay time generated by delay element 7 eliminates the effect on the transient device circuitry that occurs after the formation of the information telegram and switching the transceiver 1 from the Transfer mode to the Receive mode, In addition, the code combination 000 from the output of the counter 34 is fed to the input of the decoder 37, at the output. of which (output 27 of converter code 11) a logical zero signal is generated, coming through the element OR 28 to the second trigger input 21 This signal sets the trigger 21 to the zero state. Thus, as a result of the automatic generation of a parity pulse, the number of video pulses of each bit channel O, and channel 1 is always even (see Fig 4) a. This provides the possibility of bit-wise control of information at the control point. In addition, the device makes it possible to exclude possible operator errors when counting You enter the number of single characters in the 1-digit discharge code and manually assign the required check character, for example, by soldering jumpers. All this information is provided.

formula of invention

1 o Device for transmitting information from a mobile object, containing a transceiver connected to an antenna, the output of which is connected via a pulse shaper to the first inputs of the first and second triggers and connected to the first input of a block of meters to the first input of the pulse distributor, and to the counting input of the meter block, controlled generator. the output of which is connected to the second inlet of the transceiver, the first outputs

the block of meters is connected to the respective 3 inputs of the converter of the code, the first outputs of which are connected to the second inputs of the pulse distributor, the third trigger, the AND element, the OR element, the AND-YE element and the delay element, which is P5 e. By the fact that, in order to improve the reliability of the transmitted information, the device includes: 1.: - NTA-NES, the output of the first trigger is connected to the third input of the pulse distributor, to the first input of the first Element AND-NAND and to the first input of the AND element whose output is connected to the first control input direct oscillator, an output of first AND-NO soy .dinen to a second input controlled

generator, first output distribute -40 to the second multiplexer inputs, pulse output l is connected to the first decoder and multiplexer output to the third trigger input and to the first one are outputs of the converter input of the second NAND element, code output.

element I, the second output of the code converter is connected to the second input of the second NAND element, second: i output of the pulse distributor is connected to the second input of the first AND element, the third output of the code converter is connected to the first inputs of the third and fourth elements NAND, the second The inputs of which are connected to the output of the pulse generator, the fourth output of the code converter is connected to the first input of the element,

OR, the output of which is connected to the second input of the third trigger, the outputs of which are connected to the third inputs of the third and fourth elements AND-NOT, the outputs of which are connected to

pulses are connected to the second input of the OR element, the last output of the counter block via the Delay element

25 is connected to the third input of the second trigger; the fifth output of the conversion code is connected to the third input of the first trigger; the second inputs of the first and second trigger are connected

30 to the tire of zero potential.

2o The device according to 1, that is, that the code converter is made on the block by the third inputs of the first and second AND-NES elements, the output of the shaper 35, the decoder and the multiplexer. the decoder inputs, the first inputs of the multiplexer and the memory block are the inputs of the code converter, the outputs of the memory block are connected to

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FIG.

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