SU1247901A1 - Device for transforming coordinates - Google Patents

Abstract

The invention is intended for converting the voltages of the SSCT sensors specifying the orthogonal components of the input vector into voltages for the SSCT receivers corresponding to the coordinates of the vector rotated by a binary code angle. The device provides enhanced conversion accuracy. It contains digitally-controlled dividers 1, 2, input 3, 4, summing 5, 6, decoupling 7, 8, output 9, 10 amplifiers, switches 11-18, scaling resistors 19-50, code storage register 51, quad selector 52 The device implements the equation of rotation of the vector on the plane at a given angle, which is stored in register 51. Contours 1-5-7 and 2-6-8 realize the approximate tangent function of the half angle. Output amplifiers 9, 10 form the required dependencies, taking into account the number of the quadrant. 1 il. “(L Bx1 Bx G 37 to 4;

Description

one

The invention relates to computing and can be used to convert the voltage of a SCRT sensor specifying the coordinates of the input vector to voltages for the SCRT receiver corresponding to the coordinates of the vector rotated by the angle (argument) specified by the binary code.

The aim of the invention is to improve the accuracy of the conversion.

The drawing shows a diagram of a device for converting coordinates.

The device for converting coordinates includes digital-equalizers 1 and 2, made in the form of resistive matrices R-2R, operational amplifiers, input 3 and 4, summing 5 and 6, output 7 and 8 and output operational amplifiers 9 and 10, switches 11-18, scaling resistors 19-50, code storage register 51, quad selector 52, outputs 53 and 54.

The coordinate transformation is based on the use of the equations of vector rotation by the angle Q given by the code

and UgCos © + and sine, x, | h

Uj Uj.cos0 - Uj sin6.

where Ug and C. are the voltages coming from the SCWT sensor. Equation (1) for the first quadrant converts to

and

at

; Us + (u, + u,) tg-J

and, - and, - (id + c) of the prototype, the value of the tangent was replaced by a linear function KB, which at K 0.85 created a fault of formation ± 2.5%. In this device, to reduce this error, the tangent of the half angle is replaced

- ,. where Q is 0.705882,

addiction

6 0.294118 in the range of 0-1 angle. This reduces the reproduction error of the Ц and Uj to. When operating in four quadrants, the signs of the magnitudes and angle codes change as follows:

In the I quadrant (0-90 °) U., U5-t- (Uc + Uj):

,

and, and, - (and, + c).

In the II quadrant (90-180)

tg tt fti LTr about. (0)

(u, + u,) p - (- p0 -; and and - - (and + and)

with G-6 (1-0)

in the third quadrant ((-90) - (and n "(n - i).

    1-6 (1-®)

and -i + (and -i) q and ,,. and,; one() .

In the IV quadrant (0-90 °)

and, and, - (and, and,) -0 .0

B &

a ©

(s-u.) 1

The device works as follows.

From the computer or digital computer, the input parallel binary code proportional to the value of the rotation angle in four quadrants enters the storage register 51 of the code. A positive value of the angle in the range of 0-180 ° corresponds to a direct code, and a negative value in the same range is optional. The two most significant bits define the value of the quadrant, the remaining bits represent the angle within the quadrant. The switches 11, 12, 17, 18-with the codes of quadrant 00 and 11 are in position I, and with codes of quadrant 01 and 10 - in position II. Switches 13. and 14 are in position T, if a 0. Switch 15 is in position I, switch 16 is in position II with c 0.

From the SCRT sensor, the cosine voltage enters the amplifier 3 through the resistor 19 and is summed or subtracted with the output voltage Uj supplied to the same amplifier 3 through the resistor 21 and switch 11. In both positions of the switch 11, the addition (subtraction) is performed at a constant scale that is equal to one. From the output of the amplifier 3, the voltage goes to the direct input of the amplifier 5. At the same time, the voltage from the output of the amplifier 7 goes to the inverting input of the amplifier 5, which together with the scaling resistors 27-30

performs the function of algebraic summation, as well as amplifying 6 with resistors 31-34.

The voltage U is fed to the analog input of the first digital-to-power divider 1, the outputs of which form currents proportional to code 0 and its complement (1-0). Depending on the quadrant number, the direct or complementary outputs of the divider 1 are connected via switch 13 to amplifier 7, at the output of which a desired fractional-rational dependence approximating the tangent is formed. Similarly, the second circuit works (amplifiers 6.8 and divider 2).

At the outputs of amplifiers 9 and 10, for each of the four quadrants, the presented dependences are formed that realize the rotation of the input vector by a given angle.

The coordinate conversion device can be used in vector builder mode with a digital-to-analog output. To do this, connect a comparator to output 54 that controls the serial approximation register connected to the digital input of the converter. After balancing in the register, a code proportional to the argument is established, and at output 53 a voltage proportional to the module. vector.

Claims (1)

Invention Formula A device for converting coordinates that contains the first input operational amplifier, the inverting input of which is connected through the corresponding scaling resorie stor with its output and with the first information input of the device, the second input operational amplifier inverting in the Scope of which is connected through the corresponding scaling resistors with its output and with the second the information input of the device, the first and second digital-equalizable dividers, made in the form of resistive matrices R-2R, the first and second propagating e amplifiers, between the output and the inverting input of which the corresponding scaling resistors are included, the first output operating amplifier, the inverting input of which ten 15 20 25 2479014 connected via appropriate scaling resistors to the output of the first isolating amplifier, to the second information input of the device, to the zero potential bus, and to the output of the first output - operational amplifier, the non-inverting input of which is connected to the bus, zero potential and to the outputs the first and second switches, the inputs of the first switch are connected to the output of the first decoupling amplifier and to the zero potential bus, and the inputs of the second switch - with the second information input of the device and with a zero potential bus, the second output operational amplifier, the inverting input of which is connected through the appropriate scaling resistors with the output of the second output amplifier and with the first information input of the device, and with the output of the second in the output operational amplifier, the non-inverting input of which is connected to the zero potential through the corresponding scaling resistors and to the outputs of the third and fourth cross the switches, the inputs of the third switch are connected to the output of the second isolating amplifier and the zero potential bus, and the inputs of the fourth switch to the first information input of the device and to the bus of zero potential, the output of the first output operational amplifier through a corresponding scaling resistor and connected to it in series five the switch is connected to the inverting and non-inverting inputs of the second input operational amplifier, the output of the second output operational amplifier through the corresponding scaling resistor and the sixth switch connected in series with it are connected to the inverting and non-inverting inputs of the first input operational amplifier, the code storage register, the outputs of the two higher bits of which are connected to the inputs of the quadrant selector, and the outputs of the remaining register bits are connected respectively to the code inputs first and second digital equalizers, the output of the selector 35 40 45 50 55 pa quadrants are connected to the control inputs of the second, fourth, fifth, and sixth switches, the control input of the first switch is connected to the inverse output, and the control input of the third switch to the forward output of the higher bit of the code storage register, the non-inverting inputs of the first and second input operational amplifiers are connected to the zero potential bus through appropriate scaling resistors, characterized in that, in order to improve the accuracy of the conversion, the device contains the first and second sum the amplifiers, the seventh, eighth, ninth, and ten switches, with the output of the first input operational amplifier connected to a non-inverting input, and the output of the first converting amplifier to the inverting input of the first summing amplifier whose output is connected to the analog input of the first digitally guided divider, the output of the second input op amp is connected to a non-inverting input, and the output of the second decoupling amplifier is connected to the inverting input of the second Compiler G.Osipov Editor N.Gorvat Tehred M.Hodanich Proofreader M.Samborska Order 4128/50 Circulation 671 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 five Q 0 5 Q The summing amplifier, whose output is connected to the analog input of the second digitally controlled divider, the first output of the first digital to analog divider is connected via the seventh switch to the inverting input of the first amplifier and its non-inverting input connected to the zero potential bus, and the second output of the first digital-controlled signal the divider is connected via the eighth switch to the non-inverting input of the first decoupling amplifier and to its inverting input; the first output of the second one is digitally controlled The divider is connected via the ninth switch to the inverting input of the second developing amplifier and c. its non-inverting input connected to the zero-potential bus, the second output of the second digitally-controlled divider is connected via a ten switch to the non-inverting input of the second output amplifier and its inverting input, the direct output of the second highest-priority code storage register is connected to the control inputs seventh, eighth, ninth and tenth switches.