SU1246409A1 - Device for generating the correcting signal - Google Patents

Abstract

The invention relates to television and can be used in scanning and raster correction circuits for CRT. The device for eliminating the reprogrammable Permanent Storage Unit is simplified. In the input parameter registers block (BR) 1, the constants a, b, c are written, which determine the corresponding constant, sawtooth and parabolic components of the correction signal (SCS), respectively. These e, b.c of the SCS determine, respectively, the horizontal size, the degree of keystone and pincushion correction of the vertical lines of the television raster. The BR 1 constant is fed to the first accumulation adder (NS) 2, the step-sawtooth signal from its output goes to the subtractor 3, to the other input of which BR 1 receives the constant b. The signal from the subtractor 3 goes to the second HC 4. The adder 5, to which the HC signal and the constant a are received, forms the signal D a + KS (b - tl (- K21 CH) containing all the necessary SCS. The generated signal is converted to latitude -pulse modulator 8 and enters the correction output stage 9, Shaper 6 frame pulses and shaper 7 write pulses ensure consistent operation of the device blocks. 6 ill. Jin "nm i (L 1C 4 Od 4 O Vyma / laurel ./line

Description

The invention relates to television technology and can be used in the composition of scanning and raster correction circuits of information display devices on electron-beam tubes.

The purpose of the invention is to simplify the device by eliminating the reprogrammable Permanent Storage Unit.

Figure 1 shows the structural electrical circuit of the device for generating a correction signal; in FIG. 2, the same, first and second accumulating adders} in FIG. 3 — the same, of a pulse-width modulator; figure 4 is the same, the driver pulses to write; on fig.Z - the same, the block of registers of input parameters; 6 shows timing diagrams for the operation of the device.

The device contains a block of 1 registers of input parameters, the first adder 2, subtractor 3,

The dimensions determine the horizontal size, the degree of keystone and pincushion distortion correction of the vertical lines of the television raster-.

5 Constant with the second output of block 1 is fed to the first input of the first accumulating adder 2, in which, the formation of an increasing step-sawtooth signal,

10 definable by implantation

D - |: .c (1)

1 and

where n is the number of recording pulse from the beginning of the television frame; 15 N. - the number of recording pulses per frame interval.

In the particular case, n can take the value of the line number, and N 20 is, respectively, the number of lines in one field (half frame). During the reverse of the vertical scan, the register 11 (figure 2) of the first accumulating adder 2 is reset.

the second accumulating adder 4, sum- 25 As a result, at the first input is binary 5, shaper 6 frames

pulse shaper 7 pulses

records, latitude-pulse modulator

(PWM modulator) 8 and output stage

9 corrections .30

The first 2 and second 4 accumulating adders (figure 2) contain the binary adder 10 and the register 11.

PWM modulator 8 (fig.Z) contains

The first adder 10 at the first time after resetting the register 11 is a constant C, and at the second input is a null code combination, after the first write pulse the constant c is present on both inputs of the binary adder 10, after the second write pulse on the first input of the binary adder 10 there is a constant c .

subtractive counter 12, decoder 13, 35 ° to the second input - 2s, etc. the element OR-HE.14 and the inverter 15. For-. With the output of the first accumulator worldizer 7. record pulses (figure 4). adder 2, the signal defined by the output contains a delay element 16, by inverting (1), is fed to the second. torus 17, element 18, inverter 19 and subtractor 3 input, to the first input

40

element and 20.

Unit 1 registers the input parameters (fig.Z) contains the first 21, second 22 and third 23 registers.

A device for generating a correction signal operates as follows.

B. Block 1 of the input parameter registers, prior to the start of operation of the device (for example, when the power is turned on), three constants a, b, c are written, which are represented by 6-8-bit binary codes and determine the corresponding constant, sawtooth and parabolic components, respectively. forming a device signal. When operating as part of a display device, the indicated components of the output signal of the proposed device are 45

which the constant b comes from the first output of block 1. As a result, a signal is generated at the output of subtractor 3.

D b.- K cn, (2).

nm

where k

50

55

a scale factor taken into account by the mutual shift of the bits of the input subtractor 3 and the output pin of the first accumulating adder 2.

For example, when connected. 1,2, ..., K-th bits of the output bus of the first accumulating adder 2, respectively 0.1, ..., K + 1-th bit of the input bus of the subtractor 3, the coefficient k, is equal to two. The specific value of k. Is determined by the size of the blooyard, the horizontal size, the degree of correction of the keystone and pillow distortions of the vertical lines of the television raster are determined.

Constant with the second output of block 1 is fed to the first input of the first accumulating adder 2, in which, the formation of an increasing stepped sawtooth signal,

detectable by implantation

D - |: .c (1)

1 and

where n is the number of recording pulse from the beginning of the television frame; N. is the number of write pulses per frame interval.

In the particular case, n can take the value of a line number, and N is, respectively, the number of lines in one field (half frame). During the reverse of the vertical scan, the register 11 (figure 2) of the first accumulating adder 2 is reset.

As a result, at the first input of the binary adder 10 at the first moment after the reset of register 11 there is a constant C, and at the second input there is a zero code combination, after the first write pulse the constant c is present at both inputs of the binary adder 10, after the second write pulse at the first binary input adder 10 present constant c.

which the constant b comes from the first output of block 1. As a result, a signal is generated at the output of subtractor 3.

D b.- K cn, (2).

nm

where k

a scale factor taken into account by the mutual shift of the bits of the input subtractor 3 and the output pin of the first accumulating adder 2.

For example, when connected. 1,2, ..., K-th bits of the output bus of the first accumulating adder 2, respectively 0.1, ..., K + 1-th bit of the input bus of the subtractor 3, the coefficient k, is equal to two. The specific value of k is determined by the block size of the device and the standard of decomposition of the television system in which the proposed device operates. With a constant size of eight, and a broadcast decomposition standard (312.5 lines in a half frame)

K-4 ..

From the output of the subtractor 3, the signal B is fed to the first input of the second accumulating cyNiMaropa 4, at the output of which a signal of the form is formed

 , c,), (3)

which is then added to the constant in the adder 5 with the constant .a with the weight coefficient K ,; implemented by hardware is similar to the implementation of the coefficient K by mutual shift of the tire bits. At the output of the adder 5, a signal is generated

, (B), (4)

containing all the necessary components. you are a constant component, a sawtooth and a parabolic component.

 From the output of the adder 5, the signal D. is fed to the second (informational) input of the PWM modulator 8, which converts the codes arriving at its information input into a signal with pulse-width modulation, which is then fed to the output stage 9 of the correction. The WL module TPP 8 can be executed as an example, according to the scheme shown in FIG. In this case, the signal from the output of the adder 5 is written to the subtractive counter; 12 according to the write pulse from the first output of the imager 7 write pulses. At the end of the write pulse subtractive, the counter 12 starts counting the clock pulses arriving at its clock input through the element OR NOT 14.. When the subtractive counter 12 reaches the state 00 ... 00 at the output of the decoder. 13, performed, for example, in the form of an OR-NOT element, a logical level 1 is formed, prohibiting further clock pulses through the OR-NOT element 14. Thus, the duration of the pulse generated at the output of the inverter 15 is determined by the suppression

 V ..

(five)

where the pulse duration is in-. pisi;

one). .- pre-recorded in the counter information; clock period.

five . For normal operation of the device, it is necessary to form two time-shifted write pulses so that the recording of the signal from the output of adder 5 to the PWM modulator 8 will occur later than the end of the calculations by accumulating adder 2 and adder 5. In the former, the write pulses from horizontal flyback pulses are formed

J5 two recording pulses corresponding to the front and rear edges of the reverse pulse, and the duration of the generated pulses is determined by the value of the delay and / element.

Q 16 delay (figure 4). The write pulses are formed by the first AND 18 and second AND 20 elements of. forward and delayed reversing pulses. For a better understanding of the sequence of work.

5 blocks of the device in Fig.6 are shown. timing charts explaining the work- Device for generating a correction signal, in Fig. 6 "- a reverse fly-back pulse (output pulse 6 and framing pulse 6); 6 sg - page pulses at the input of the former. 7 recording pulses, in FIG. B, 2 - recording pulses respectively on the second and first outputs of the imager

 7 write pulses, figo - clock frequency pulses, figure 6 shows CONDITIONALLY; (in the form of voltage steps) the signal at the output of the first accumulated dego of adder 2, on

 Fig. 6g shows the signal at the output of read 3, in Fig. 6u the signal at the output of the second accumulating adder 4, at Fig. b. the signal at the output of adder 5, and at fig. - modulator B.

Claims (1)

Invention Formula % 0 A device for generating a correction signal, comprising a frame pulse former, the input of which is the input of reverse frame pulse, the first accumulating adder, a pulse-width modulator, the first input of which is the input of clock pulses, and the output is connected to the output of the output pulse correction stage, characterized in that, for the purpose of simplification; device by eliminating the reprogrammable Permanent Storage Unit, a write pulse shaper and serially connected input parameter registers are entered into it, a subtractor, a second accumulating adder and an adder, the input of the input parameter registers block and the second and the third outputs are connected respectively to the first input of the first accumulating sum torus and the second input of the adder, the output of which is connected to the second input of a pulse-width modulator, the third input of which is connected to the first output of the recording pulse generator, the input of which is the input of the horizontal return pulse, and the second output is connected to the second inputs of the first and second accumulating adders, the third inputs of which are connected to the output of the personnel pulse generator, and the output of the first accumulating adder is connected to the second input of the subtractor. Fig.Z FIG. H 5 6 Editor O. Golovach Compiled by I. Gracianska Tehred L. Oleynik Proofreader V. But ha Order L024 / 57 Circulation (S24 Subscription  VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, 4/5 Raushsk nab. Production and printing company, Uzhgorod, Projecto st., A